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anee_anil
Adventurer
Adventurer
6,593 Views
Registered: ‎01-16-2008

how to delay the output?

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Hi all,

My input is of 10Mhz (100ns). Clock of the CPLD is 80MHz.
There is 5-bit Delay selection line which selects the input to be delayed by number of clock cycles.
e.g., 00101 delays output by 5 clock cycles 12.5*5 = 62.5ns
but my code does not work after 00011 selection. Please anybody help me out.
Here is my code.



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fiber_splitter is
port(clk : in std_logic;
inp_wave : in std_logic;
delay_sel : in std_logic_vector(4 downto 0);
out_wave : out std_logic);
end fiber_splitter;

architecture Behavioral of fiber_splitter is

begin
process(clk)
begin
--if(clk'event and clk = '1') then
case delay_sel is
when "00000" => out_wave <= inp_wave;
when "00001" => out_wave <= inp_wave after 12.5ps;
when "00010" => out_wave <= inp_wave after 25.0ps;
when "00011" => out_wave <= inp_wave after 37.5ps;
when "00100" => out_wave <= inp_wave after 50.0ps;
when "00101" => out_wave <= inp_wave after 62.5ps;
when "00110" => out_wave <= inp_wave after 75.0ps;
when "00111" => out_wave <= inp_wave after 87.5ps;
when "01000" => out_wave <= inp_wave after 100.0ps;
when "01001" => out_wave <= inp_wave after 112.5ps;
when "01010" => out_wave <= inp_wave after 125.0ps;
when "01011" => out_wave <= inp_wave after 137.5ps;
when "01100" => out_wave <= inp_wave after 150.0ps;
when "01101" => out_wave <= inp_wave after 162.5ps;
when "01110" => out_wave <= inp_wave after 175.0ps;
when "01111" => out_wave <= inp_wave after 187.5ps;
when "10000" => out_wave <= inp_wave after 200.0ps;
when others => null;
end case;
--end if;
end process;
end Behavioral;


Thanks in advance
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1 Solution

Accepted Solutions
eilert
Teacher
Teacher
8,173 Views
Registered: ‎08-14-2007

Hi anee_anil,

sure it's synthesizable:

 

initial_delay_counter:process (reset, clock) is

begin

  if reset ='1' then

    initial_delay_done <= '0';

    delay_count          <= delay_clocks;  -- defined in a generic;

  elsif rising_edge(Clock) then

    if initial_delay_done = '0' then

        delay_count <= delay_count -'1';

        if delay_count = zero then   -- zero defined as constant

          initial_delay_done <= '1';

        end if;

    end if;

  end if;

end  initial_delay_counter;

 

 Hope there are no typos or missing end ifs.

 

Now you can use the initial_delay_done flag as an enable for any circut that has to be delayed.

The all types have to be std_logic or std_logic_vector.

 

As a pure initial delay, this code runs only once, and is neither restartable, nor can the delay time be changed during runtime.

But this can be added quite simply.

 

Have a nice synthesis

 

  Eilert

 

View solution in original post

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7 Replies
mcgett
Xilinx Employee
Xilinx Employee
6,588 Views
Registered: ‎01-03-2008

The code that you posted isn't doing what you say it should be doing.

 

1) The code are using the "after" syntax.  This is only valid for simulation and won't synthesize

2) The "clk'event" syntax is commented out, but the sensitivity list only has "clk" te process will be run on both rising and falling edges of clk.  Changes to delay_sel and inp_wave will have no effect if clk is not toggling

3) You post said "nS", but the code has "pS"

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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anee_anil
Adventurer
Adventurer
6,586 Views
Registered: ‎01-16-2008

Thanks for your reply.

 

How should i go ahead to get the required output.

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eilert
Teacher
Teacher
6,584 Views
Registered: ‎08-14-2007

Hi anee_anil,

for delaying signals in a FPGA you can either use a counter or a shift register/FIFO.

 

The counter is good for initial delays.

 

The FIFO can be used for continuous signal delays even of multiple signals.

You need a counter here too, for the write_enables, and once the delay threshold is reached, you start reading the FIFO.

 

Remember, that you can only delay a signal by integer multiples of the clock period. (with some tricks you can add a half period too, but for the beginning stay to the simple sokution.)

 

 

Have a nice synthesis

  Eilert

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anee_anil
Adventurer
Adventurer
6,573 Views
Registered: ‎01-16-2008

hi eilert,

Is that synthesizable.

 

Give piece of code..

Thanks

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anee_anil
Adventurer
Adventurer
6,572 Views
Registered: ‎01-16-2008

hi eilert,

Is that synthesizable.

 

Give piece of code for initial delay by number of clock cycle..

Thanks

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eilert
Teacher
Teacher
8,174 Views
Registered: ‎08-14-2007

Hi anee_anil,

sure it's synthesizable:

 

initial_delay_counter:process (reset, clock) is

begin

  if reset ='1' then

    initial_delay_done <= '0';

    delay_count          <= delay_clocks;  -- defined in a generic;

  elsif rising_edge(Clock) then

    if initial_delay_done = '0' then

        delay_count <= delay_count -'1';

        if delay_count = zero then   -- zero defined as constant

          initial_delay_done <= '1';

        end if;

    end if;

  end if;

end  initial_delay_counter;

 

 Hope there are no typos or missing end ifs.

 

Now you can use the initial_delay_done flag as an enable for any circut that has to be delayed.

The all types have to be std_logic or std_logic_vector.

 

As a pure initial delay, this code runs only once, and is neither restartable, nor can the delay time be changed during runtime.

But this can be added quite simply.

 

Have a nice synthesis

 

  Eilert

 

View solution in original post

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jprovidenza
Voyager
Voyager
6,555 Views
Registered: ‎08-30-2007

Here's a Verilog snippet that may move you in the proper direction....

 

reg [3:0]     dly_data;

wire [7:0]    data_sel;

 

// create a pipeline of the delayed data values

always @(posedge clk)

  dly_data <= {dly_data, inp_wave};

 

// gather the desired data into a nice bus for easy selection

assign data_sel = {2'b0, dly_data, inp_wave}

 

// select the proper output data

assign out_data = data_sel[delay_sel];

John Providenza

 

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