cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
technovlsi
Explorer
Explorer
3,414 Views
Registered: ‎01-30-2011

how to get output waveform of dds logicore through modelsim?

sir, i am using DDS logicore.setting up its parameters iget the vhdl code,but when i simulate it through isim,it gives error,can't get the output. how will i get it sir?

0 Kudos
3 Replies
eilert
Teacher
Teacher
3,412 Views
Registered: ‎08-14-2007

Hi,

maybe it would be a good idea to post at least the error message to give a hint what may be the cause for the error.

 

Have a nice simulation

  Eilert

0 Kudos
technovlsi
Explorer
Explorer
3,405 Views
Registered: ‎01-30-2011

module test;

 

            // Inputs

            reg clk;

            reg we;

            reg [27:0] data;

 

            // Outputs

            wire [5:0] cosine;

            wire [5:0] sine;

 

            // Instantiate the Unit Under Test (UUT)

            dds_compiler_v4_0 uut (

                        .clk(clk),

                        .we(we),

                        .data(data),

                        .cosine(cosine),

                        .sine(sine)

            );

 

 

           

            initial begin

            clk =0;

            forever#10 clk=~clk;

            end

initial begin                   

                        we = 1;

                        data = 60;

 

                        // Wait 100 ns for global reset to finish

                        #100;

       

                          we = 1;

                        data = 70;

 

                        // Wait 100 ns for global reset to finish

                        #100;

       

                          we = 1;

                        data = 50;

 

                        // Wait 100 ns for global reset to finish

                        #100;

       

                          we = 1;

                        data = 80;

 

                        // Wait 100 ns for global reset to finish

                        #100;

       

                        // Add stimulus here

 

            end

     

endmodule

 

ERROR:HDLCompiler:559 - "C:/Documents and Settings/Administrator/Desktop/test.v" Line 37: Could not find module/primitive <dds_compiler_v4_0>.

 

sir , in the bold line error is coming.

 

0 Kudos
ywu
Xilinx Employee
Xilinx Employee
3,401 Views
Registered: ‎11-28-2007

Please do not cross-post the same question. It makes harder for people who try to help. I replied to the same question on the DSP board below:

 

http://forums.xilinx.com/t5/DSP-Tools/error-in-simulation-of-DDS-LOGICORE/m-p/177372/highlight/false#M4427

 

 

 

Cheers,
Jim
0 Kudos