06-17-2011 11:12 AM
Hi~
In my project, the processor is connect with a memory. The instuctions and data should be put into the memory before starting the processor. My question is how to initialize the memory(put the instructions and data into memory ) in a few cycles?
please tell me the procedures in VHDL, just like "readmemb" in verilog.
06-17-2011 11:19 AM
You should specify whether the memory to be loaded is internal to the FPGA, or external.
If the memory is internal to the FPGA (e.g. PicoBlaze), then the memory contents are naturally embedded in the configuration bitstream.
Perhaps some additional details would help provide you with a useful answer. For example, is this a custom board design or an off-the-shelf development board?
-- Bob Elkind
06-18-2011 07:23 PM
Hi~, eteam00,
thank you for your answer.
I just wanna simulate my processor in my project with ISE and ISIM, What I need to do is designing a ram, and take it as the memory. I think first I need to input the instructions and data into the ram in my testbench, my problem is How to initialize the memory in VHDL...
06-20-2011 09:01 AM - edited 06-20-2011 09:01 AM
@peter_123 wrote:
Hi~, eteam00,
thank you for your answer.
I just wanna simulate my processor in my project with ISE and ISIM, What I need to do is designing a ram, and take it as the memory. I think first I need to input the instructions and data into the ram in my testbench, my problem is How to initialize the memory in VHDL...
You didn't answer Bob's questions.