I want to write data to a register in the FPGA via jtag. I use the BSCAN_VIRTEX4 and write a tcl to write the data. But it did not work. This is the first time that I use the tcl and jtag. I don't know why? The promblem is the tcl part or the verilog part? The following is my code, I want to write data to the "mux_reg".
BSCAN_VIRTEX4 #( .JTAG_CHAIN(3)) BSCAN_VIRTEX_inst ( .CAPTURE(), .DRCK(clk), // Data register output for USER functions
.RESET(rst), // Reset output from TAP controller .SEL(), .SHIFT(shift), // SHIFT output from TAP controller .TDI(tdi), // TDI output from TAP controller .UPDATE(), .TDO(o_tdo) // Data input for USER function