02-15-2015 01:12 AM
i aim to implememt i2c lines (SDA and SCL) on xilinx FPGA. the FPGA would be in slave mode.
i am planning to declare the lines as inout in my top level.
also, i intend to have the scl and sda lines as follows -
assign SCL = control_scl ? 1'bz : scl_out;
assign SDA = control_sda ? 1'bz : sda_out;
what i want to confirm is that will the above construct be automatically inferred by xilinx (or synplify) as a tristate buffer or will i have to use a xilinx tri-state primitive specifically mimicing the above functionality?
if i put the sda and scl lines in z state, then will the master be able to take control of the lines and drive them? what voltage levels should the z state lines be in so that the master i2c driver can still drive them? i intend to use a 3.3v i2c programmer cable ...
02-15-2015 07:57 AM
First, the names of your control signals are not very informative. In the code you posted a '1' on the "control" indicates you want to tristate the signal., which is counterintuitive for someone looking at the logic. I typically use a more informative name like "drive_SCL" (1 = output active, 0 = output high Z) or "tristate_SCL" (1 = output high Z, 0 = output active).
Next you should realize that I2C is an open-drain interface. So you don't really need to have data and clock signals in addition to the drive controls. Never drive these signals high. Only let the external resistor pull them up as described in the specification. The only exception is if you are making a master interface that connects point to point with slave(s) that don't require clock stretching. Thein it is OK to actively drive SCL all the time.
A typcal I2C interface looks more like:
assign SCL = tristate_SCL ? 1'bZ : 1'b0; // never drive high, only low or tristate
assign SDA = tristate_SDA ? 1'bZ : 1'b0;
For a slave interface that doesn't require clock stretching, you should never need to drive SCL.
02-15-2015 11:27 AM
thanks for the reply gabor.
i'll see if i am driving the i2c lines high or not and/or the interface i have is actually open drain and hass the PU resistors for the i2c slave.
however the snippet i showed, will it be automatically inferred as a tri-state buffer by XST and/or Synplify or do i have to specifically instantiate a tri-state buffer in its place ...?