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alperuzgec
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Registered: ‎11-23-2008

illegal multiplexer construct

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Hello,

 

i'm getting this error while bitstream process. How can i fix this?

 

ERROR:Xst:1770 - Illegal multiplexer construct found in equation of signal <t_141>. At least one multiplexer input does not have the correct width. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com.
make: *** [implementation/system.ngc] Error 1
Done!

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eilert
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Registered: ‎08-14-2007

Hi,

it's a error message from the XST synthesis tool. And it's quite clear:

 

At least one multiplexer input does not have the correct width.

 

So take a look at your sources, where a bus is too wide or too narrow at one of your multiplexors.

 (Hint: It maybe near signal t_141)

 

 

Have a nice synthesis

  Eilert

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eilert
Teacher
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7,960 Views
Registered: ‎08-14-2007

Hi,

it's a error message from the XST synthesis tool. And it's quite clear:

 

At least one multiplexer input does not have the correct width.

 

So take a look at your sources, where a bus is too wide or too narrow at one of your multiplexors.

 (Hint: It maybe near signal t_141)

 

 

Have a nice synthesis

  Eilert

View solution in original post

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alperuzgec
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Registered: ‎11-23-2008

i looked at files, your reply is true. i fixed it. but new error is occured. these caused by memory reading and writing.

 

 

ERROR:Xst:2587 - Port <PLB_MRdDBus> of instance <plb_my_core_0> has different type in definition <plb_my_core>.

 

i didn't any change in port files manually. only added memory i/o code.  couldn't find any document about 'MRdDBus'.

 

Note: Answer database says this bug was fixed.  earlier 10.1 version. I'm using 11.1

Message Edited by alperuzgec on 09-14-2009 06:59 AM
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eilert
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Registered: ‎08-14-2007

hi,

this looks more like a EDK related problem.

Have you checked/compared the types of  Port <PLB_MRdDBus> in the mentioned instances? Are they really the same or not?

Maybe the core was generated wrong?

 

Can't say anything more detailed without suficcient data.

 

Have a nice synthesis

  Eilert

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alperuzgec
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Registered: ‎11-23-2008

in core MPD file;

PORT PLB_MRdDBus=PLB_MRdDBus, DIR = I, VEC = [0:(C_MPLB_DWIDTH-1)], BUS=MPLB

 

in core VHDL file;

PLB_MRdDBus : in  std_logic_vector(0 to C_SPLB_DWIDTH-1);

 

i changed  SPLB to MPLB in VHDL file. 

 

i'm synthesizing now. which one is true? How can i learn this? 

Message Edited by alperuzgec on 09-15-2009 12:50 AM
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eilert
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Registered: ‎08-14-2007

Hi,

since you are designing complex PowerPC based systems (Why else should you use cores with a PLB-Interface?)  you surely have an idea how the different I/O-cores communicate with the processor (and each other).

So the buswidth for each core has been determined by you. In the generated VHDL files you find the buswidth declared with GENERIC values. (e.g. C_SPLB_DWIDTH) I guess the S stands for Slave and the M is for Master.

 

See in your definition files how these values are selected.

In VHDL it is mandatory to connect signals of the same type.

So  a 16-bit standard_logic_vector only fits to another 16-bit standard_logic_vector. (simplified)

 

If the definitions you made are correct, everything should be OK.

If it's just some tool problem you can probably fix it the way you tried.

 

If a generated core has a different buswidth than the other devices you need to check if is this allowed for the PLB. (I don't know, never worked with it)

If it is allowed, and the tools stumble over it, you may need some bus converter module, that is able to e.g. connect a 16-Bit PLB with a 32-Bit PLB. If such a thing exists. (Whishbone uses such converters)

 

Maybe there are better ways, but then you should open a new thread in one of the EDK related Forum.

 

Have a nice synthesis

  Eilert

 

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