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Registered: ‎01-19-2010

input is not same as output?



I was testing a new SPARTAN 3AN based board. Just to test that I was able to program the FPGA, I declared a top level entity with two signals. One input and one output. Input was connected to a 40MHz clock and output is connected to a floating test point. In architecture, I have one statement saying input signal is assigned to output signal. After generating .mcs file and programing the FPGA with it, when I was observing the input and output pins (test points) on the circuit board using oscilloscope, at input it was a good 40MHz clock. At output test point, it was about 40MHz clock, but the clock was rolling across the screen when triggerred with input clock. Meaning, the output clock was about 5-10 Hz slower than input clock. The FPGA (since, VHDL did not have any idea about nature of input signal, so PLL or clock managers were not present in FPGA) should just act as pass through for that signal, even with use of IBUF or OBUF, I do not see how the signal would be changed by FPGA.


Any ideas on how this could occur?



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Registered: ‎02-27-2008



Well, it simply can not occur.


I suggest you simulate your code, or open it in FPGA_Editor and see what you have (in your design).


I suspect you will have nothing at all in your design, and you are triggering on noise.

Remeber the tools are very efficient, and if you have a mistake, they will optimize the design until there is nothing to do (if you have no logic function, they may decide there is nothing to do).


Read all warnings and errors from the synthesis, and also from the place and route, and from the bitgen operations.




Austin Lesea
Principal Engineer
Xilinx San Jose
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