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Scholar ronnywebers
Scholar
8,011 Views
Registered: ‎10-10-2014

interfacing standard parallel ADC with Zynq

Hello,

 

I'm wondering what would be the best approach to interface a 'standard' TTL parallel ADC, like a 12 - 16 bit wide, with clock ranging from 10 to 80MHz. So just a bunch of datalines and a single clock. The continuous data needs to be streamed to the DDR3 memory using AXI-4 DMA. Preferably the ADC clock can come from an external oscillator (TCXO), so it is definitely asynchronous to the internal clocks of the PL

 

- would a good approach to build a custom IP that converts this data to an AXI-4 Stream?

- or would it be possible to re-use the video IP blocks for this somehow?

- how best to handle the clock domain crossing ? put an async fifo on the AXI-4 stream

- what if I want to add some AXI-4 Lite control interface to this custom IP block (for example to enable/disable data flow, or to perform some math on the data (shifting bits up / down, ...) , how do I handle the clock domain crossings between the AXI-4 lite registes and the ADC data manipulation? The AXI-4 lite will run on one of the PS_FCLKx clocks, while the custom IP will generate an AXI-Stream synchronous to the external TCXO

 

Is there any tutorial on interfacing a simple parallel ADC? Didn't find any ... and I searched well ... strange, 'cause many data acquisition applications require such a design.

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