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Visitor
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Registered: ‎10-28-2018

iserdese2 simulation outputs always logic 0

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I have built a test harness for the iserdese2 for 8 bits, but the logic outputs are always 8'h00.  LVDS freq is 300 MHz, divided frequency is 37.5 MHz, test input is 8'hA5, but the output remains zero throughout the simulation.  Attached are the verilog source and simulation traces for review in the hope that I have missed something it its configuration.

LVDSReceiverTest.jpg

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Visitor
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Registered: ‎10-28-2018

In the end I did determine the problem.  While I meticulously made certain that the serdes was held in reset for several clock pulses, I was only looking at the lvds clock, not the much slower divclk (pixel_clk in my test case).  After ensuring that the serdes was held in reset for the slower clock, it started to work.

Silly mistake on my part.  Thanks to all who took the time to view the request for help. 

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Visitor
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Registered: ‎10-28-2018

In the end I did determine the problem.  While I meticulously made certain that the serdes was held in reset for several clock pulses, I was only looking at the lvds clock, not the much slower divclk (pixel_clk in my test case).  After ensuring that the serdes was held in reset for the slower clock, it started to work.

Silly mistake on my part.  Thanks to all who took the time to view the request for help. 

View solution in original post

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Guide
Guide
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Registered: ‎01-23-2009

While it could be the reset as you say, it could also be the GSR time. Some of the Xilinx primitive cells model the GSR - the global set reset that exists in the FPGA. When the FPGA powers on, it goes through a whole configuration process; the last step of which is the assertion of the GSR that resets most of the cells which hold state (including the IOB/DDR/SERDES registers).

The simulation models of these primitive cells (and the STARTUP module) model this GSR time at the "beginning" of each simulation - essentially these cells behave as if they are held in GSR for some fixed amount of time at the beginning of the simulation. In your early simulation, you may have been trying to use the ISERDES during this time. Once you lengthened the reset, you may have pushed past this GSR time and the ISERDES started working...

Avrum

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Visitor
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Registered: ‎10-28-2018

Great point, thank you.  Is there any way to expose the GSR such that it can be accounted for in startup logic?

I.e:

reg gsr_init = 1'b1;    // initialized to 1 by GSR?

always @( posedge system_clk ) begin

    if( gsr_init == 1 && 'other_factors' ) begin

....

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