08-21-2016 10:46 PM
In VCU 108 Board, the board differential clock of 300MHz is provided for DDR4 IP core clocks.
Can I choose other differential clocks: pcie refclk, sysclk_125 ?
or use PLL to generate a lower frequency clock?
08-21-2016 11:10 PM - edited 08-21-2016 11:13 PM
I would like to know why you want to use alternate clock . Use the same clock as thats tested with MIG design .
You need to generate the MIG again with your new clock constraint .
Follow the guideline and according to that you can make required change.
However i not seeing any benefit to use alternate clock .
check clocking section in MIG product Guide
Here is some important document which can help you