lower DDR4 clock rate on VCU 108 / ultrascale?

[bowen_fu]

Hi,

In VCU 108 Board, the board differential clock of 300MHz is provided for DDR4 IP core clocks.

eg.

c0_sys_clk_p

c0_sys_clk_n

Can I choose other differential clocks: pcie refclk, sysclk_125 ?

or use PLL to generate a lower frequency clock?

Thanks!

[balkris]

I would like to know why you want to use alternate clock . Use the same clock as thats tested with MIG design .

You need to generate the MIG again with your new clock constraint .

Follow the guideline and according to that you can make required change.

However i not seeing any benefit to use alternate clock .

check clocking section in MIG product Guide

Here is some important document which can help you

http://www.xilinx.com/products/design_resources/mem_corner/ddr4.htm
http://www.xilinx.com/Attachment/Xilinx_Answer_60305_2014_3_.pdf
http://www.xilinx.com/support/answers/60305.html
https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0061-ultrascale-memory-interface-ddr4-ddr3-hub.html
http://www.xilinx.com/support/documentation/ip_documentation/ug086.pdf

[bowen_fu]

because we are hitting calibration fail a lot. The timing slack of mmcm_clk is bad: -1.7ns.
The utilization is already quite high, like 75%