07-10-2018 07:21 PM
I want to do machine learning in Xilinx FPGA, how to transfer the code written in Python or C++ to FPGA.
Should I write the code directly with HDL language, or is there any other convenient method? what is the specific process?
07-10-2018 10:09 PM
@zxyglx_ That is not a productive approach - simply attempting to move the code.
You could go two ways:
- Use SDSOC and let Vivado identify what can be accelerated for you
- Use HLS (my preferred method)
The most effective way is to identify modules in your code that could have streaming inputs/outputs and then recode them from scratch in HLS, perhaps with a bit of copy/paste from existing sources.
No HDL (Verilog/VHDL) is strictly necessary.