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weilings
Explorer
Explorer
3,698 Views
Registered: ‎03-08-2012

newbie's question about variable's characteristics

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Hey, I have a code as follow:

process(clk)

variable list_head : element_ptr := NULL;
variable temp_elem : element_ptr := NULL;
variable last_clk : std_logic := 'U';
begin

.......

end process

 

 

my question:  1. the 'list_head' and the other variables are initialized everytime when the process is triggered?

                          2. is 'list_head' visible out of the process? If the 'list_head' is changed to a signal, is it visible out of the process?

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hgleamon1
Teacher
Teacher
4,620 Views
Registered: ‎11-14-2011

1. No. Initialisations are power-on values only (and quite distinct from a reset value). Your question shows quite a "software" mentality. You need to think about it in terms of hardware (FFs). How would it be "initialised"? How useful would it be if it were "initialised" every clock (as you have a clocked process)?

 

2. No, variables cannot be used outside of their defining process. Making the variable a signal will allow it be used by other processes (note that you should only assign a value to a signal in ONE process).

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle

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hgleamon1
Teacher
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4,621 Views
Registered: ‎11-14-2011

1. No. Initialisations are power-on values only (and quite distinct from a reset value). Your question shows quite a "software" mentality. You need to think about it in terms of hardware (FFs). How would it be "initialised"? How useful would it be if it were "initialised" every clock (as you have a clocked process)?

 

2. No, variables cannot be used outside of their defining process. Making the variable a signal will allow it be used by other processes (note that you should only assign a value to a signal in ONE process).

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle

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weilings
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Registered: ‎03-08-2012

Thank you very much for your reply.

As for the "Hardware" mentality, I will try.

What do you mean by "assign in ONE process"? Do you mean we can "read" the signal in many processes, but can "write" in ONE process? 

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hgleamon1
Teacher
Teacher
3,663 Views
Registered: ‎11-14-2011

Regarding signal assignments, that's exactly what I mean.

 

It's a situation that trips up many people, newbies and more experienced designers (although usually with more complex designs) and can be a source of simulation frustration.

 

Good luck.

----------
"That which we must learn to do, we learn by doing." - Aristotle
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