02-04-2015 02:57 PM
i have a large RTL design which has about 200+ files (.vhd modules, .v modules etc.). it's basically an asic design that i need to port to FPGA.
i have filelists for the design. but they are more for vcs, spyglass tools format.
so my question is - if i have such a big design and i want to open it in xilinx, how do i do so? should i manually add the 200+ files in the heirarchy?
i know there is an import custom file list option but it doesnt seem to pick my file lists (perhaps because of other constructs in the list). so do i need to change the filelists to adhere to xilinx syntax? if so, any details about xilinx supported file lists online? and can xilinx pick file lists that point to other files which then point to the actual file/dir?
what other optiions do i have to open large designs/file-lists in xilinx ISE?
please note - i am not worried about non-fpga constructs at this moment, just want to be able to see the design heirarchy without any missing modules etc. i am using xilinx ISE 14.1
02-04-2015 06:26 PM
02-04-2015 10:13 PM
thanks. i had already looked at the link.
the files i have are in different folders. so the question is -
are things like $relative_path_variable/foldername/file.v type of syntaxes supported by ISE?
can we simply include directories (like we do in vcs) and all the files in the dir will be automatically included in the heir?
is there a more detailed list of syntaxes supported by the ISE import custom file list function?
please point me to it ...
02-05-2015 12:28 AM
In "Add source" you can select all files in a directory at once and add them to the project.
Check if this helps.
02-05-2015 12:53 PM - edited 02-05-2015 12:54 PM
i am only able to select files by ctrl+left click. however is there any option where files present in a particular folder can be included directly? (doing ctrl+left click for 200+ files is not ideal)
02-05-2015 03:28 PM - edited 02-05-2015 03:30 PM
Scripts are your friend. Even in ISE. It's easier in Vivado but still works in ISE.
XST needs your RTL files to be read in like:
verilog work "foo.v"
verilog work "bar.v"
The filenames can be a full path (relative paths suggested).
We call our file "fpga.prj"
Massage your filelist too look like the above.
Then you need and an "fpga.xst" file:
It looks like
run -ofmt verilog -ifn fpga.prj ...
The "..." is a list of XST options that you desire for XST.
Use the help / documentation / dummy run though with a small example in the gui to create/massage this file.
Then run xst with
xst -ifn fpga.xst -ofn fpga_xst.log
You're good to go. Bonus for tying it all together with Make, and automagically creating you're list of file depedencies.
02-05-2015 06:41 PM