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Visitor haiqings
Visitor
3,881 Views
Registered: ‎06-09-2010

out signal and in signal share the same pin

I just found I defined a output signal and input signal in VHDL and assigned them to the same pin(they should not share the same pin logically). but systhize does not give any error message, so, this will make that pin become an inout signal? or my output signal will drive that input signal?

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3 Replies
Instructor
Instructor
3,870 Views
Registered: ‎08-14-2007

Re: out signal and in signal share the same pin

What do you mean "assigned to the same pin?"  Your UCF gives two nets the same LOC constraint?  I would think that would creat an error, either during translate or Map.  But you could run "implement design" to see this yourself.  If you need a pin to be bidirectional you must define an inout port.

-- Gabor
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Visitor haiqings
Visitor
3,863 Views
Registered: ‎06-09-2010

Re: out signal and in signal share the same pin

I did not use UCF file, I used "attribute loc of signal" to assign pin number, it passed all the processes of translate and fit.

 

I just found that software give me the warning message and automatically moved the one of the signal to another location.

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Xilinx Employee
Xilinx Employee
3,860 Views
Registered: ‎01-03-2008

Re: out signal and in signal share the same pin

The use of bi-directional signals is a common practice with an tri-state output buffer (OBUFT) and an input buffer (IBUF).  There is a combined element called an IOBUF in the Xilinx libraries.  The use of bi-directional signals requires that the system understand when the internal logic is allowed to drive the signal and when the external logic is allowed to drive the signal. 

 

It is not clear from your original post if you fully understand the concept of bi-directional signals.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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