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part selection for many fmc cards

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I recently started a new job in wireless lab and we are trying to purchase an FPGA board. I don't have a wireless background, but based on my labmate's need, he wants to generate 16 I/Q signals on FPGA(each I,Q signal is 8 bit) and output in parallel(so that we can convert those 16 digital signals to analog).

 

So I think we need total 16*2*8=256 pins. I've never tried converting digital signals to analog signals... maybe I need to use FMC card? 0)So do I need a board that has FMC card slots whose total number of width is at least 256? 

 

Zedboard, for instance, seems to have one FMC slot that is 34bit. We probably won't use many LUTs on FPGA, so I don't think we need a fancy high-end FPGA. I just want to know 1)whether how people normally extract digital signal out and convert it to analog signal and 2)whether it's usual to extract such large number of pins.

 

Thanks in advance.

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Scholar u4223374
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Re: part selection for many fmc cards

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RFSoC might be a waste, but it's still worth looking into - even if you only use 10% of the FPGA logic, if having one chip instead of 17 (FPGA + 16 DACs) means that your PCB costs a quarter as much to build and 1/10th as much to populate, then it might be cheaper to just accept the wasted resources. It also greatly increases your upgrade options...

 

JESD204 requires at least one high-speed transceiver. Normally each FMC slot has a bunch of these routed to it (if the FPGA supports that), so if you're designing your own FMC card then you could potentially put a couple of TI's AFE7685 (each uses a single JESD204 interface with eight transceivers). However, this still leaves you requiring 32 transceivers, which is going to mean a pretty expensive FPGA.

 

Can you get some more information about the requirements? Getting 16 8-bit DAC channels is trivial; a single AD5390 can do 16 14-bit channels over two wires (I2C) but slowly (maybe as fast as a few kHz). On the other hand, getting 16 8-bit channels at 5.8GSPS requires at least 742.4Gb/s bandwidth, and that's where the problems lie - an FPGA I/O pin will normally give you around 500Mbps, or 10Gbps for one of the transceivers (each transceiver is two pins). This requirement then translates into either 1500 I/O pins or 75 transceivers, both of which will be hideously expensive.

 

If your project genuinely requires the latter, then I'm pretty sure that spending $10K+ on an RFSoC is going to be the cheapest option for you. If your project only requires maybe 10MHz DACs, then we can look at appropriate interfacing - 10MHz is the sort of range where a single LVDS pair (two wires) can potentially drive 4+ channels.

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Scholar u4223374
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Re: part selection for many fmc cards

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16 channels is quite a lot.

 

One option would be to just buy an XCZU29DR and be done with it. The ZU29DR is one of Xilinx's new RFSoC chips - a fast ARM processor, a large FPGA fabric, and (on that specific chip) 16 14-bit 6.554GSPS DACs. I don't know what the pricing is on these, but I would expect that it's not cheap.

 

Alternatively, a lot of the fast (ie RF-speed) DACs use the JESD 204B interface, which allows them to use far fewer than 16 pins per transmitter - depending on data rates. This might be cheaper, but it'll add a lot of parts to the BOM and a lot of space to the PCB. XIlinx developed the RFSoC largely to avoid that.

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Re: part selection for many fmc cards

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@u4223374

 

Thanks. We are looking for a board that can simply accommodate many DACs/ADCs with a minimal FPGA logic. So RFSoC may be waste...

 

To use JESD interface, is there any requirement for a board? For instance, to use JESD interface, does it require to have one FMC slot per a DAC/ADC? Thanks!

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Re: part selection for many fmc cards

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RFSoC might be a waste, but it's still worth looking into - even if you only use 10% of the FPGA logic, if having one chip instead of 17 (FPGA + 16 DACs) means that your PCB costs a quarter as much to build and 1/10th as much to populate, then it might be cheaper to just accept the wasted resources. It also greatly increases your upgrade options...

 

JESD204 requires at least one high-speed transceiver. Normally each FMC slot has a bunch of these routed to it (if the FPGA supports that), so if you're designing your own FMC card then you could potentially put a couple of TI's AFE7685 (each uses a single JESD204 interface with eight transceivers). However, this still leaves you requiring 32 transceivers, which is going to mean a pretty expensive FPGA.

 

Can you get some more information about the requirements? Getting 16 8-bit DAC channels is trivial; a single AD5390 can do 16 14-bit channels over two wires (I2C) but slowly (maybe as fast as a few kHz). On the other hand, getting 16 8-bit channels at 5.8GSPS requires at least 742.4Gb/s bandwidth, and that's where the problems lie - an FPGA I/O pin will normally give you around 500Mbps, or 10Gbps for one of the transceivers (each transceiver is two pins). This requirement then translates into either 1500 I/O pins or 75 transceivers, both of which will be hideously expensive.

 

If your project genuinely requires the latter, then I'm pretty sure that spending $10K+ on an RFSoC is going to be the cheapest option for you. If your project only requires maybe 10MHz DACs, then we can look at appropriate interfacing - 10MHz is the sort of range where a single LVDS pair (two wires) can potentially drive 4+ channels.

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Re: part selection for many fmc cards

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@u4223374  Thanks a lot! What I am still confused is the relationship between pins and transceiver. What is transceiver?
If it requires 75 transceivers and you said each transceiver is two pins... it translates to 150 I/O pins which sounds really reasonable.

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Scholar u4223374
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Re: part selection for many fmc cards

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@moon5756 For very high data rates, some FPGAs have integrated high-speed transceivers. These are fixed-function (well, semi-configurable - but definitely not normal FPGA fabric) blocks designed to get signals into and out of the FPGA as fast as possible; while a pair of regular I/O pins might get you 1Gbps in LVDS mode, a transceiver can deliver upwards of 30Gbps depending on which version it is.

 

The downside is that transceivers are power-hungry and expensive to build. The small and cheap FPGAs don't have any at all. Getting 75 would require one of the following chips:

 

XC7VX550T (13.1Gbps maximum per transceiver)

XCKU15P (44 are 16.3Gbps, 32 are 32.75Gbps)

XCVU125 (40 are 16.3Gbps, 40 are 30.5Gbps)

XCVU5P (all 32.75Gbps)

 

The cheapest of these is the XCKU15P. Prices start at around $3700 US on Digikey, for the bare chip. In terms of development boards, the VCU118 gives you 24 32.75Gbps transceivers on a single FMC+ port, which would technically meet the data rate requirements for 16 8-bit channels at 5.8Gsps (if you can find appropriate transceiver chips).

 

Developing a PCB for these transceivers is also easier said than done - at these speeds you do need to pay a lot of attention to impedance calculations.

 

As I said above, you really need to decide exactly what your requirements are. If getting over 700Gbps bandwidth is essential, that can be done - but it's going to be a very expensive and challenging project. If you spend $15,000 setting up a development platform and then find that actually your project only needed 1Mbps data rate on each channel (16*8*1Mbps = 128Mb/s, which is easily manageable by the cheapest Spartan 7) then you've just wasted a lot of time and money.

 

Similarly, you do need to have a close look at your LUT requirements. "not many LUTs" and "700Gbps" do not appear likely to fit together. You definitely won't be doing much processing offline (you can't get data out of any storage medium fast enough to keep up with the RF side). Data is going to have to be generated on-the-fly, which probably means a couple of pretty substantial cores.

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Re: part selection for many fmc cards

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@u4223374

Thanks again for the detailed explanation. I have a much better understanding now.

 

(Question 1)
http://warpproject.org/trac/wiki/HardwareUsersGuides/WARPv3
Here's the previous board the team was using a while ago. The main reason we are trying to buy a new one is that it has only two DACs and two ADCs not that the sampling rate is slow; which means 100MSPS ADCs and 170MSPS DACs are good enough. I think we are not there yet to process everything on the fly. We probably generate all the signals from the PC and send it through FPGA to RF. PC-FPGA interface could be a bottleneck, but at the moment, we don't even care about it I guess.

 

For example,
https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html#overview
this board has one FMC HPC connector and one FMC LPC connector. In order for this board to support 16 DACs or 16 ADCs, each FMC connector needs some FMC modules that have 8 channels, am I correct?
Something like
http://www.hitechglobal.com/FMCModules/16-bit_AD-DA.htm
but 8 channels instead of 4 channels.

 

(Question 2)
Also can you re-explain the relationship between the number of I/O pins and the transceiver? For instance if we have an output wire "[7:0] result", I thought each bit is connected to one pin. As you said, if I/O pin has 500Mbps, does it translate to 8*500Mbps=4Gbps?

 

Thanks a lot!

 

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Re: part selection for many fmc cards

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@moon5756 Sorry for the slow reply.

 

(1) That definitely helps to put a limit on the maximum performance required. However, I would strongly recommend considering the PC-FPGA bottleneck early; it's going to be pretty disappointing to spend a lot of money on this board and then find that it's not suitable. Also, that FPGA is a pretty substantial one even by modern standards - if you're using a significant proportion of that for two ADCs and two DACs, then you will definitely need to think about available resources on the new board.

 

With the ZC706, each card would need to have a total of at least 16 channels. Whether that's 8-channel DAC + 8-channel ADC or one 16-channel ADC card and one 16-channel DAC card doesn't really matter. As an example, Abaco's FMC116 (16-channel 125MSPS ADC) and FMC216 (16-channel 312.5MSPS DAC) might do the job nicely. However, these are both designed for FMC-HPC; you would have to check whether either will work on the LPC slot.

 

(2) For LVDS, each bit from an output actually connects to two pins on the chip. When the bit is a zero, one pin goes high and the other pin goes low. When the bit is a one, the opposite happens. For a bunch of technical reasons, this allows far higher speeds than you could easily achieve with single-ended I/O (ie one pin per bit of the output). If you had a [7:0] output (ie 8-bits) connected to LVDS pins, signalling at 500Mbps, then this would take 16 pins (2 pins per bit) and the data rate would be 8*500 = 4Gbit/s.

 

 

 

 

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