09-09-2011 04:00 AM
simple, (or maybe not so simple) question:
Is it possible to use a DCM to phase align two clocks that are independent but have almost the same frequency?
In particular, suppose you have two 80MHz clocks (frequency identical up to 1 out of 10^4).
One is a "nice" 50% duty cycle clock coming from a quarz that is supposed to really clock the FPGA. The other are 1ns long pulses (with repetition rate 80MHz) that are coming from a photodiode (and amplified to proper logic levels).
Now we can tune the clock from the quarz such that it nearly has the same frequency as the clock from the laser.
Now let's phase align them. How do we have to feed the two clocks into the DCM such that the DCM output is in phase with the clock from the laser?
Thanks to all for your help!
09-09-2011 07:52 AM - edited 09-09-2011 07:53 AM
You will need two DCMs, and external phase-frequency detectors (built from LUTs and DFF).
The reference goes to the phase detector LUT, along with a selected DCM CLK0 output. Both DCM's are run using the phase shift feature: while one increments the phase, its output is either leading or lagging the reference. If it is behind, the phase shift is incremented. If the phase is lagging, it is decremented. When you get to 360 degrees (255), or you get to 0 degrees (0), and you need to go further, you have been moving the other DCM so it is ready to be switched in (using the BUGMUX) to continue incrementing, or decrementing.
We used this method to do clock recovery. It isn't very fast (can not track a large frequency difference, nor can it track the jitter on the clock).
A nice little trick by using two DCMs to extend the phase shift beyond o to 360 degrees.
09-11-2011 02:40 AM
many thanks for your fast answer!
A neat trick, indeed!
I must confess, though, with only a few rookie designers that are all physicists by training, this may take us some time to implement. Have you published a xilinx white paper or xapp about this?
Hmm, I am thinking... , then, in the end it may be easier to clock the entire FPGA using the clock signal from the laser. Or only the relevant part of the FPGA core...
In our case, the FPGA core is a 666MHz pulse pattern generator - implemented on a spartan 3E. Our design normally runs on 666 MHz (1.5 ns) and the base clock is 83.33 MHz (666 MHz / 8). We use a DCM to generate clocks for the different serializer stages: x1, x2, x4. What matters to us are the last output stages, those that read the programmed pulse sequence from a FIFO and push them into serializer stages to achieve the final output speed. So, it would be sufficient to run only this last part of the design on the clock coming from the laser.
This means we have to convert the photodiode pulses from the laser into a 'proper' 50% duty cycle colck signal using analog electronics: amplifier + low pass + coupling capacitor (or some external PLL chip?).
Another simpler solution to generate a 'proper' 80 MHz clock from the photodiode pulses may be this:
1. just amplify the photodiode pulses to the required logic level and feed them directly into the FPGA (ideally fast comparator and a DAC to adjust the trigger level).
2. From this, generate a div2 clock using:
always @ ( posedge photo_diode ):
div2_clk <= ~div2_clk
This div2 clock should have 'proper' 50% duty cycle and should be good enough to be used as input clock for a DCM.
3. Feed the div2_clk into a DCM. The 2x clock output will be the original 80MHz clock but with 50% duty cycle.
This is a bit primitive but should be easy to implement ...
Are there better solutions?
Dr. Helmut Fedder
3. Physics Institute
University of Stuttgart