02-16-2017 11:02 PM
I am working on an academic paper and because of that I need to have some information about dimensions of CLBs in micrometer (even very roughly). I know such things are usually commercial secret, but I hope that is not very critical thing. Actually what I need is number of FF per unit of area, then by knowing sizes of CLB I can calculate it.
02-17-2017 06:04 AM
Are you after an average value (ie area of chip divided by number of flip-flops), or one that applies only to the logic sections (ie ignoring the Zynq PS, BRAM, DSP slices, transceivers, I/O, etc)?
The first is fairly easy; in the worst-case you could just buy a chip (one of the models with an exposed die, not the fully-encapsulated ones), do the area measurement yourself, and divide by the number of flipflops that Xilinx lists. No doubt other people on here could measure their own chips if they have time and the inclination.
The latter is much harder; I'd be surprised if Xilinx was willing to hand over that information without an NDA.
02-17-2017 06:13 AM - edited 02-17-2017 06:15 AM
I think (total die area / total number of FFs) is not precise, because BRAMs, IOs, routhing switch boxes,... are also counted in area. I need to know dimensions of CLB, so calculate (area of CLB/number of FFs inside CLB).
I need this number for a research about soft errors.
02-17-2017 10:57 AM - edited 02-17-2017 10:57 AM
02-17-2017 11:59 AM
Thanks @muzaffer , I appreciate if you can give a source that can be mentioned as a reference in paper. Even if giving such number for latest FPGA generations is not possible, for older generations, like 3rd, 4th or 5th are also useful.