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moncefou
Visitor
Visitor
460 Views
Registered: ‎05-17-2021

port has illegal connections

i realised this project :

Capture.PNG

but i get this error that i dont understand :

[Synth 8-5535] port <s_axi_aclk> has illegal connections. It is illegal to have a port connected to an input buffer and other components. The following are the port connections :
Input Buffer:
	Port I of instance \OV_7670_v2_0_S_AXI_inst/camera/your_instance_name/clkin1_buf (IBUFG) in module <OV_7670_v2_0>
Other Components:
	Port C of instance \OV_7670_v2_0_S_AXI_inst/axi_rdata_reg[31] (FDRE) in module OV_7670_v2_0
....
	

 

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4 Replies
dpaul24
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449 Views
Registered: ‎08-07-2014

@moncefou ,

You have posted the BD screenshot which does not convey the needed information.

Please posted the screenshot of the 'Elaborated Design' and show the port, clock signal and bufffer for which the error is generated.

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moncefou
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Registered: ‎05-17-2021

thanks this is the elaborated design , the blue line is the port connections

1.PNG
3.PNG
2.PNG
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dpaul24
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Registered: ‎08-07-2014

@moncefou ,

 port <s_axi_aclk> has illegal connections. It is illegal to have a port connected to an input buffer and other components.

Sorry I cannot track down where the illegal connection is occurring!

------------FPGA enthusiast------------
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bruce_karaffa
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Registered: ‎06-21-2017

Is there an input buffer in your camera block?

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