problem in simulation and synthesis

[akkisubhu]

why does the ouput remain  uninitialised plz help

[awillen · Accepted solution]

akkisubhu, did you read my reply in this thread? Did you understand it? You have the same problems in this code. We can't help you if you don't communicate with us.

Also, if you don't even put in the effort to apply proper indentation, why should we put in the effort to help you?

[akkisubhu]

Sorry for your inconvenience !

but as said i reframed the code and now its giving proper behavioural simulation but the problem arises in post translate simulation as in for simple counter example the post translate model depicts that counter stays in initial state itself plz could u help me out with  this problem

[akkisubhu]

output remains uninitialized in post translate simulation it does not proceed to further states

[awillen]

Post-translate simulation works fine for me. Is the clock signal behaving correctly in the waveform window?

Your code still has a couple of problems, though:

1. count >"11" is always false, because count is only 2 bits wide.
2. If you have a continuous signal assignment to counter_state, then you shouldn't give it an initial value (because counter_state is not a register). The same applies to output signals in your testbench.
3. Do not use the packages std_logic_arith or std_logic_unsigned. Replace them with numeric_std, and use the types unsigned and signed instead of std_logic_vector when you want to model an unsigned or signed number.
4. Use rising_edge(clk) instead of clk'event and clk='1'.