UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Reply
Explorer
Posts: 265
Registered: ‎08-13-2010

problem in 'while' loop in VHDL

I want to make a modulus program by VHDL code, 
I have made this code 


library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity modulus is 
port (clk : in std_logic; 
x: in std_logic_vector(2 downto 0); 
y: in std_logic_vector(2 downto 0); 
p: out std_logic_vector(5 downto 0)); 
end modulous; 
architecture modulus_arch of modulus is 
signal n : std_logic_vector(2 downto 0); 
signal s1: std_logic_vector(5 downto 0); 


begin 
main: process(x,y,n,clk) 
begin 
if(rising_edge(clk)) then 
while s1<=x loop 
n<=n+"001"; 
s1<=n*y; 
end loop; 
p<=x-y*(n-"001"); 
n1<=n; 
end if; 
end process main; 
end modulus_arch;
 


there is no error indeed, 
compilation,simulation, synthesize , implementation have been done , 

but when i want to see in test bench wave form following warning has been seen 


//WARNING:Simulator:29 - at 10.000 ns(1): Warning: There is an 'U'|'X'|'W'|'Z'|'-'// 

and dont show the desired output 

here i gave "110" in 'x'.& "011" in y, 
i want to calculate 5 mod 3
so output should be 2
but i found '6hXX'


Instructor
Posts: 9,048
Registered: ‎08-14-2007

Re: problem in 'while' loop in VHDL

In the hardware "n" should start up as zero.  In simulation, however there is

no initialization value in your module, so it starts up as 'U' or 'X' and because

it depends on itself never gets out of this state.  Try adding an initialization

value to "n" in the signal declaration.

 

HTH,

Gabor

-- Gabor
Explorer
Posts: 265
Registered: ‎08-13-2010

Re: problem in 'while' loop in VHDL

now i initialize 'n' and 's',

but the problem is same

output is 'u'

Explorer
Posts: 127
Registered: ‎11-26-2008

Re: problem in 'while' loop in VHDL

Are you sure the while loop is doing what you think it is? Remember that you are describing hardware, not programming a mircoprocessor.

 

To synthesize a while loop, the synthesizer will need to unroll the loop, essentially recreating the loop contents in hardware for each path through it - and since the synthesizer probably wont be able to infer the number of times to unroll your loop, I can't really see how you have been able to synthesize your code in the first place?...

Historian
Posts: 6,500
Registered: ‎02-25-2008

Re: problem in 'while' loop in VHDL

 


rourabpaul wrote:

I want to make a modulus program by VHDL code, 
I have made this code 


library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity modulus is 
port (clk : in std_logic; 
x: in std_logic_vector(2 downto 0); 
y: in std_logic_vector(2 downto 0); 
p: out std_logic_vector(5 downto 0)); 
end modulous; 
architecture modulus_arch of modulus is 
signal n : std_logic_vector(2 downto 0); 
signal s1: std_logic_vector(5 downto 0); 


begin 
main: process(x,y,n,clk) 
begin 
if(rising_edge(clk)) then 
while s1<=x loop 
n<=n+"001"; 
s1<=n*y; 
end loop; 
p<=x-y*(n-"001"); 
n1<=n; 
end if; 
end process main; 
end modulus_arch;
 


there is no error indeed, 
compilation,simulation, synthesize , implementation have been done , 

but when i want to see in test bench wave form following warning has been seen 


//WARNING:Simulator:29 - at 10.000 ns(1): Warning: There is an 'U'|'X'|'W'|'Z'|'-'// 

and dont show the desired output 

here i gave "110" in 'x'.& "011" in y, 
i want to calculate 5 mod 3
so output should be 2
but i found '6hXX'



Wow, that's some awful code. The sensitivity list is wrong. And you really need to understand the whole notion of non-blocking signal assignments. Signals DO NOT update in the manner that you clearly expect.

 

----------------------------Yes, I do this for a living.
Explorer
Posts: 265
Registered: ‎08-13-2010

Re: problem in 'while' loop in VHDL

"

Wow, that's some awful code. The sensitivity list is wrong. And you really need to understand the whole notion of non-blocking signal assignments. Signals DO NOT update in the manner that you clearly expect.

 


----------------------------------------------------------------
PLEASE do NOT send me a PM asking for help with your project/homework.

"

it may be my project or home work,but im expecting a solution from this site,but when u are telling about a problem

then its also necessary to indicate the problem,whats the problem in my code ?if you dnt, then you also should not poke your nose in this topic,

im have also tried this program removing 'clk' from sensitivity list,and also initialized 's1' as "000001" and 'n' as "000"  ,

but the problem is same,

u can also try this code in your simulator,

 

 

"

Are you sure the while loop is doing what you think it is? Remember that you are describing hardware, not programming a mircoprocessor.

 

To synthesize a while loop, the synthesizer will need to unroll the loop, essentially recreating the loop contents in hardware for each path through it - and since the synthesizer probably wont be able to infer the number of times to unroll your loop, I can't really see how you have been able to synthesize your code in the first place?...

"

 

is there any other process to find modulus?

 

Historian
Posts: 6,500
Registered: ‎02-25-2008

Re: problem in 'while' loop in VHDL

 


rourabpaul wrote:

"

Wow, that's some awful code. The sensitivity list is wrong. And you really need to understand the whole notion of non-blocking signal assignments. Signals DO NOT update in the manner that you clearly expect.

 


----------------------------------------------------------------
PLEASE do NOT send me a PM asking for help with your project/homework.

"

it may be my project or home work,but im expecting a solution from this site,but when u are telling about a problem

then its also necessary to indicate the problem,whats the problem in my code ?if you dnt, then you also should not poke your nose in this topic,

 


 

 

First -- I'll poke my nose where I wish.

Second -- you should not expect a solution.

Third -- the problem is your code.

 

 

 


 

im have also tried this program removing 'clk' from sensitivity list,and also initialized 's1' as "000001" and 'n' as "000"  ,

but the problem is same,

u can also try this code in your simulator,


 

 

A) clk is the only signal that should be on the sensitivity list!

B) the signal n1 is never declared anywhere, so the code doesn't even compile.

C) You should NOT use std_logic_arith, use numeric_std instead.

 

 

 

----------------------------Yes, I do this for a living.
Explorer
Posts: 265
Registered: ‎08-13-2010

Re: problem in 'while' loop in VHDL

 when i was compiling it  the n1 line must be off,otherwise it obviously doesnt compile,( im using a signal without considering it,wow im not really that such type of infant) 

actually i want to check the 'n',so i wrote that line,

and i also tried with numeric_std,but the result is same.

u can try it also in your simulator(removing 'n','x','y'),

i know you are really busy person who havnt  time to do help a learner  but hav time to poke,

i think in this case you should ignore this topic,

 

 

 

 

 

Explorer
Posts: 127
Registered: ‎11-26-2008

Re: problem in 'while' loop in VHDL

First of all, you need to remember that the code you write needs to be something that can be turned into hardware. If you do not understand this, then it's going to be very hard to write some FPGA code that actually works...

 

A modulus operator can be implemented very easily if you're doing modulus of some number, n,  that's a power of 2 - in this case you can just take out  the last n-1 bits as the result, and that's it. For any other numbers though, there is no fast way to do it in VHDL. The two best solutions I can think of is to:

 

1: Create a small state machine to perform the calculation - this will take some additional coding, and will take more than one clock cycle to complete, but it should be possible to do it pretty neatly.

2: Instantiate a divider, for instance using CoreGen - the dividers in here have a remainder output, which is the same number as the modulus. These will use more than a single clock also though, depending on the size of the operands.

 

 

But again, the most important thing is to understand what kind of hardware the different coding statements you write relate to - a good VHDL book might be able to help you with this.

Explorer
Posts: 200
Registered: ‎09-20-2007

Re: problem in 'while' loop in VHDL

[ Edited ]

Generally while loop is not recommended for synthesize, even in the for loop both the limits must be static. for example.

 

for i in 0 to 7 loop  --is a valid statement. whereas,

 

for i in  0 to user_in loop  --user_in is an input port signal is not valid.

 

BTW, what is your objective.

FPGA freak