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Adventurer
Adventurer
22,223 Views
Registered: ‎01-16-2008

pulse generator in vhdl

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Hi all,

I'm trying to do a pulse generator to be implemented in a cpld
the idea is to get an output pulse derived from a 80Mhz clock.

The frequency of the output is derived by 16-bit data and a clock.
e.g., 0000000000000001 indicates 12.5ns output frequency
0000000000000010 indicates 25ns output frequency.

The pulse width of the output is derived by 10 bit data
e.g., 0000000001 indicates 12.5ns pulse width
0000000010 indicates 25ns pulse width

and there will be 6 bit input, through which we can select 8 output ports.
when we select other signal, the previous signal should retain the data.


entity pulse_gen is
port(clk : in std_logic;
freq_data : in std_logic_vector(15 downto 0);
pulse_width_data : in std_logic_vector(9 downto 0);
wave_sel : in std_logic_vector(5 downto 0);
out_wave : out std_logic_vector(7 downto 0));
end entity;
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1 Solution

Accepted Solutions
Teacher eilert
Teacher
18,923 Views
Registered: ‎08-14-2007

Re: pulse generator in vhdl

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Hi anee_anil,

In your signal generator process you have an (up to now) unused asynchronous reset branch.

you are using the signals start and en there.

 

It would be better practice if you would use a dedicated reset signal for that purpose and put the  enabling signals in the synchronous part of your system.

 

e.g.:

 

begin

if (reset = '1') then

 --reset registers here

elsif (clk'event and clk = '1' ) then
  if (start = '1' and en = '0') then
    --generator code starts here

 

so for your question about initial delay:

create a delay_done flag, that you set to zero on reset (and whenever an initial start is required).

Then you just need a counter loop that runs once while  delay_done is still '0' and after that loop you set the flag to '1' to prevent the delay counter from running again.

That's all.

 

Another tip: use emacs for automatic line indention etc. (ctrl+c, ctrl+b), so your code becomes better readable.

 

Have a nice synthesis

  Eilert

View solution in original post

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14 Replies
Explorer
Explorer
22,201 Views
Registered: ‎04-06-2009

Re: pulse generator in vhdl

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What you are looking for actually?

 


The frequency of the output is derived by 16-bit data and a clock.
e.g., 0000000000000001 indicates 12.5ns output frequency
0000000000000010 indicates 25ns output frequency.

The pulse width of the output is derived by 10 bit data
e.g., 0000000001 indicates 12.5ns pulse width
0000000010 indicates 25ns pulse width

freq_data : in std_logic_vector(15 downto 0);
pulse_width_data : in std_logic_vector(9 downto 0);

Pulse width and the freq signifies the same - 1/Pulse Width = Freq, so why you need both?

Shantanu Sarkar
http://www.linkedin.com/pub/shantanu-sarkar/0/33a/335
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Adventurer
Adventurer
22,193 Views
Registered: ‎01-16-2008

Re: pulse generator in vhdl

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Thanks for your reply.

 

I am looking for a pulse repetition time and pulse width generation vhdl code.

I did a part of the code but that did not work.

 

with regards

ANIL

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Teacher eilert
Teacher
22,187 Views
Registered: ‎08-14-2007

Re: pulse generator in vhdl

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Hi Anil,

 show us your code and we can give you some hints.

 

Have a nice synthesis

  Eilert

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Adventurer
Adventurer
22,165 Views
Registered: ‎01-16-2008

Re: pulse generator in vhdl

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 Hi eliert,

Thanks for your response :)

 

This is my code for PRT(pulse repetition time) and PW (pulse width)

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pulse_generator is
port(clk : in std_logic;
     prt : in std_logic_vector(15 downto 0);
      pw : in std_logic_vector(9 downto 0);        -- pulse width
      wave_sel : in std_logic_vector(5 downto 0);
      out_wave0,out_wave1,out_wave2,out_wave3,out_wave4,out_wave5,out_wave6,out_wave7 : out std_logic);
end pulse_generator;

architecture Behavioral of pulse_generator is
signal count2 :  std_logic_vector(9 downto 0) :="0000000000";
signal count1 : std_logic_vector(15 downto 0) :="0000000000000000";
signal clkout, clkout1, clkout2 : std_logic;
begin
process(clk)
begin
case wave_sel is
when "000000" => out_wave0 <= clkout;
--when "000001" => out_wave1 <= clkoutb;
--when "000010" => out_wave2 <= clkoutc;
--when "000011" => out_wave3 <= clkoutd;
--when "000100" => out_wave4 <= clkoute;
--when "000101" => out_wave5 <= clkoutf;
--when "000110" => out_wave6 <= clkoutg;
--when "000111" => out_wave7 <= clkouth;
when others => null;
end case;
end process;

process(clk, pw, prt)
variable temp1 : std_logic_vector(9 downto 0);
variable temp2 : std_logic_vector(15 downto 0);
--variable count2 :  std_logic_vector(9 downto 0) :="0000000000";
--variable count1 : std_logic_vector(15 downto 0) :="0000000000000000";
begin
if (clk'event and clk = '1' ) then

temp2 := prt;
clkout1 <= '1';
count1 <= count1 + 1;
if(temp2 = count1) then
count1 <= "0000000000000000";
end if;
if(count1 <= pw) then
temp1 := pw;
clkout2 <= '1';
count2 <= count2 + 1;
if(temp1 = count2) then
count2 <= "0000000000";
clkout2 <= '0';
end if;
else
clkout2 <= '0';
end if;
end if;
clkout <= clkout1 and clkout2;
end process;
end Behavioral;

 

and this code works for single channel.

I have 8 outputs. Once the inputs are assigned to the output, it should retain the same PRT and PW even after change in the output. The new output should have the new values. like this 8 outputs should go on.

 

which logic I should use? I tried with many . I dont know how to use files in vhdl.

If possible please code for me to retain the  values at output

 

Thanks with regards

 

 

 

 

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Explorer
Explorer
22,158 Views
Registered: ‎04-06-2009

Re: pulse generator in vhdl

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entity pulse_generator is
port(clk : in std_logic;
     prt : in std_logic_vector(15 downto 0);
      pw : in std_logic_vector(9 downto 0);        -- pulse width
      wave_sel : in std_logic_vector(5 downto 0);
      out_wave0,out_wave1,out_wave2,out_wave3,out_wave4,out_wave5,out_wave6,out_wave7 : out std_logic);
end pulse_generator;
 

 

I have 8 outputs. Once the inputs are assigned to the output, it should retain the same PRT and PW even after change in the output. The new output should have the new values. like this 8 outputs should go on.

 

which logic I should use? I tried with many . I dont know how to use files in vhdl.

If possible please code for me to retain the  values at output

 


 

Still your requirement is not very clear to me.

 

What I understood you are looking for 8 Channel programmable Pulse Generator - Using the Wave_Sel you want to program the Pulse Repetation Time and Pulse Width (i.e the Freq and the Duty Cycle in other words) for respective Wave Output.

Say you have seleted like -

Wave_out0 - Freq=1MHz / Duty Cycle = 10%

Wave_out1 - Freq=2MHz / Duty Cycle = 20%

Wave_out2 - Freq=3MHz / Duty Cycle = 30%

Wave_out3 - Freq=4MHz / Duty Cycle = 40%

Wave_out4 - Freq=5MHz / Duty Cycle = 50%

Wave_out5 - Freq=6MHz / Duty Cycle = 60%

Wave_out6 - Freq=7MHz / Duty Cycle = 70% 

Wave_out7 - Freq=8MHz / Duty Cycle = 80% 

 

And you are expecting the outputs accordingly. Pl clarify if my understanding is write or wrong?

 

If this is your requirement then your code is not going to work - you need 8 Registers to store the PRT and 8 Reg to store the PW for respective Wave Outputs.

 

 

 

Shantanu Sarkar
http://www.linkedin.com/pub/shantanu-sarkar/0/33a/335
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Adventurer
Adventurer
22,148 Views
Registered: ‎01-16-2008

Re: pulse generator in vhdl

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Yes shantanu,

 

How to have a 8 register in the code that stores the PRT value.

 

anil.haladipur@gmail.com

 

Thanks

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Explorer
Explorer
22,144 Views
Registered: ‎04-06-2009

Re: pulse generator in vhdl

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Declaring Signals are nothing but Reg. As you want 8 Reg, you can use Array. 

 

In your case the logic will be something like this -


PX: Process(CLK, PRT, Wave_Sel)

Begin

If(Rising_Edge(CLk)) Then

case wave_sel is
when "000000" => Array_PRT_0 <= PRT; Array_PW_0 <= PW;
when "000001" => Array_PRT_1 <= PRT; Array_PW_1 <= PW;

when "000010" => Array_PRT_2 <= PRT; Array_PW_2 <= PW;
when "000011" => Array_PRT_3 <= PRT; Array_PW_3 <= PW;
when "000100" => Array_PRT_4 <= PRT; Array_PW_4 <= PW;
when "000101" => Array_PRT_5 <= PRT; Array_PW_5 <= PW;
when "000110" => Array_PRT_6 <= PRT; Array_PW_6 <= PW;
when "000111" => Array_PRT_7 <= PRT; Array_PW_7 <= PW;
when others => null;
end case;

End If;

End Process;


 

P0: Process(CLK, Array_PRT_0, Array_PW_0)

Variable Count0 : Std_Logic_Vector(N downto 0) := (Others => '0'); 

Begin

If(Rising_Edge(CLk)) Then

Count0 := Count0 + '1';

If(Count0 <=  Array_PW_0) Then

Wave_Out_0 <= '1';

Elsif (Count0 <=  Array_PRT_0) Then

Wave_Out_0 <= '0';

Else

Count0 := (Others => '0'); 

End If

End If;

End Process;


 

Shantanu Sarkar
http://www.linkedin.com/pub/shantanu-sarkar/0/33a/335
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Teacher eilert
Teacher
22,106 Views
Registered: ‎08-14-2007

Re: pulse generator in vhdl

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Hi anee_anil.

Think modular.

Your code works fine for one chanel, so remove everything that has to do with wave selection and make a pure one channel generator.

You may need some Write Enable signal for controlling the storage of PW and PRT values.

 

Next set up a module that instantiates eight of your one channel signal generators (for ..generate may  be useful).

and add some code that selects the access to the configuration registers for PW and PRT of each signal generator module.

 

Depending on the selection you just control the writing to the configuration registers.

e.g.:

write_enable <= (others => '0'); -- default assignment 

case wave_sel is
  when "000000" => write_enable(0) <= '1';

  when "000001" => write_enable(1) <= '1';
  when "000010" => write_enable(2) <= '1';
  when "000011" => write_enable(3) <= '1';
  when "000100" => write_enable(4) <= '1';
  when "000101" => write_enable(5) <= '1';
  when "000110" => write_enable(6) <= '1';
  when "000111" => write_enable(7) <= '1';
when others => null;
end case;

 

So the outputs will continuously generate 8 parallel signals, which can be changed on selection.

Also it is simple to add an output enable selection to the toplevel module if needed. 

 

Have a nice synthesis.

  Eilert

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Adventurer
Adventurer
22,092 Views
Registered: ‎01-16-2008

Re: pulse generator in vhdl

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Hi eilert,

 

Thanks for your reply. I have changed my code based on some extra requirement. 

 

16 bit data bus from external source gives the PRT, PW, Repetition time and delay.
Address bus specifies the 6 bit value which holds the address of the PRT, PW and Repetition and
delay .
when enable is high the CPLD will start reading the data based on the addresses and stores it in a
variable. When enable is low and start is high then the data from the variables are fetched and
based on the data, signal is generated.
The output of eight signals should simultaneously work for different inputs given
PRT : Pulse Repetition Time
PW : Pulse width
REP : how many time the output should repeat

DELAY : delay at the beginning

Here is my code that gives PRT and Pw. how to implement repetition and delay in the same code.


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.my_package.all;

entity pulse_rep is
port(data_bus : in std_logic_vector(15 downto 0);
      addr_bus : in std_logic_vector(5 downto 0);
      clk          : in std_logic;
      en          : in std_logic;
      start      : in std_logic;
      data_out0, data_out1, data_out2, data_out3, data_out4, data_out5, data_out6, data_out7 : out std_logic);
end pulse_rep;

architecture Behavioral of pulse_rep is
signal addr      : integer range 0 to 32;                -- address in integer numbers
signal rep_int : integer range 0 to 100;          -- Repetition in integers
signal clkout1, clkout2, clkout3 : std_logic;
signal PRT, PW, REP, DELAY : std_logic_vector(15 downto 0);
signal count1, count2, count3 : std_logic_vector(15 downto 0) := "0000000000000000";
signal temp : std_logic_vector(15 downto 0);
type vector_array is array(0 to 3) of
            std_logic_vector(15 downto 0);
signal memory : vector_array;            -- momory 0 to 3 of 16 bit each
begin
process(clk, en)
variable temp3 : integer range 0 to 32;
variable temp4 : integer range 0 to 100;
begin
temp3 := 0;
if en = '1' then
if clk'event and clk = '1' then
memory(addr) <= data_bus;                -- allocating incoming data to the memory
end if;
for i in addr_bus'range loop            -- address bus of
if (addr_bus(i) = '1') then            -- std_logic_vector  
temp3 := 2*temp3 + 1;                    -- to
else                                            -- integer
temp3 := 2*temp3;                            -- conversion
end if;                                        --
end loop;
addr <= temp3;
end if;

--for i in REP'range loop                  -- Repetition of
--if (REP(i) = '1') then                  -- std_logic_vector  
--temp4 := 2*temp4 + 1;                       -- to
--else                                            -- integer
--temp4 := 2*temp4;                            -- conversion
--end if;                                        --
--end loop;
--rep_int <= temp4;

PRT <= memory(0);
PW <= memory(1);
REP <= memory(2);
DELAY <= memory(3);
end process;

process(clk, en, start)

variable temp1, temp2 : std_logic_vector(15 downto 0);
begin
if (start = '1' and en = '0') then
if (clk'event and clk = '1' ) then

temp2 := prt;
clkout1 <= '1';
count1 <= count1 + 1;
count3 <= count3 + 1;
if(delay = count3) then
clkout3 <= '1';
end if;
if(temp2 = count1) then        
count1 <= "0000000000000000";
end if;
if(count1 <= pw) then
temp1 := pw;
clkout2 <= '1';
count2 <= count2 + 1;
if(temp1 = count2) then
count2 <= "0000000000000000";
clkout2 <= '0';
end if;
else
clkout2 <= '0';
end if;
end if;
end if;
data_out0 <= clkout1 and clkout2;

end process;
end Behavioral;

 

kindly help me to generate delay and repetition.

Thanks in advance. Hoping for positive reply

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Teacher eilert
Teacher
18,924 Views
Registered: ‎08-14-2007

Re: pulse generator in vhdl

Jump to solution

Hi anee_anil,

In your signal generator process you have an (up to now) unused asynchronous reset branch.

you are using the signals start and en there.

 

It would be better practice if you would use a dedicated reset signal for that purpose and put the  enabling signals in the synchronous part of your system.

 

e.g.:

 

begin

if (reset = '1') then

 --reset registers here

elsif (clk'event and clk = '1' ) then
  if (start = '1' and en = '0') then
    --generator code starts here

 

so for your question about initial delay:

create a delay_done flag, that you set to zero on reset (and whenever an initial start is required).

Then you just need a counter loop that runs once while  delay_done is still '0' and after that loop you set the flag to '1' to prevent the delay counter from running again.

That's all.

 

Another tip: use emacs for automatic line indention etc. (ctrl+c, ctrl+b), so your code becomes better readable.

 

Have a nice synthesis

  Eilert

View solution in original post

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Adventurer
Adventurer
11,259 Views
Registered: ‎01-16-2008

Re: pulse generator in vhdl

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Hi eilert,

 

Can you please generate a code for delay and repetition. everything is messing up when i try to build up.

 

 

Thanks

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Highlighted
10,098 Views
Registered: ‎02-09-2011

Re: pulse generator in vhdl

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hiiiiiiii

i need a pulse generator program with all parameters changable..............

like duty cycle, pulse width, etc etc.............

could you please help me..........

Tags (1)
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Teacher eilert
Teacher
10,091 Views
Registered: ‎08-14-2007

Re: pulse generator in vhdl

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Hi,

let me guess...

The first parameter you are about to change will be the designers name, before submitting it?

 

 

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Historian
Historian
10,077 Views
Registered: ‎02-25-2008

Re: pulse generator in vhdl

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@vnpavankumarkalaga wrote:

hiiiiiiii

i need a pulse generator program with all parameters changable..............

like duty cycle, pulse width, etc etc.............

could you please help me..........


Contact me via PM for my consulting rate.

 

----------------------------Yes, I do this for a living.
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