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Explorer
Explorer
8,476 Views
Registered: ‎12-01-2010

questions about Traffic Generator in MIG

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Hi, I am a green hand in MIG. After I generated the DDR3 SDRAM core, I found there was no input to the use interface. Then I saw the Traffic Generator.

QQ截图20120806180933.jpg

It seems that traffic generator can give data and command to the user interface, but I don't know how to use it, even after I read the code in it. I also searched on the forums, but no resolution was found. Furthermore, there are no traffic generator files in the project window. Only can be found in the project files. Though I added them to the project, it maked no sense. Does anyone know how to use it?

Thanks in advance.

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1 Solution

Accepted Solutions
Advisor eilert
Advisor
10,557 Views
Registered: ‎08-14-2007

Re: questions about Traffic Generator in MIG

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Hi,

if I correctly understood the user guide document the testbench is synthesizable as well.

A rare thing, but in this case it makes sense, since a DDR3 interface needs to be verified (and sometimes slightly adjusted) by measurements. 

 

But this can easily be answered if you provide a correct UCF file for the IOBs LOC constraints and simply start an implementation flow. If that runs without errors you just have to wait for your board.

 

Have a nice synthesis

 

  Eilert

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8 Replies
Advisor eilert
Advisor
8,464 Views
Registered: ‎08-14-2007

Re: questions about Traffic Generator in MIG

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Hi,

according to the diagram, the traffic generator might consist of one or more processes in the ddr3_sim_tb_Top source.

In that testbench something must be connected to the memory controller instance, that's probably what you are looking for.

With the parameters BEGIN_ADDR and END_ADDR it seems that you are able to define the memory range where this code is placing the data patterns.

 

On page 55 of the UG406 you will find more details about the traffic generator usage.

 

Have a nice simulation

  Eilert

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Explorer
Explorer
8,456 Views
Registered: ‎12-01-2010

Re: questions about Traffic Generator in MIG

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I've added the example_top.vhd into the project and now it works with a traffic generator. However, the simulation doesn't seem right. I found this in init_mem_pattern_ctr.vhd. Should I change this parameters in order to control the input? Or in other files?

FAMILY : STRING := "SPARTAN6";
TST_MEM_INSTR_MODE : STRING := "R_W_INSTR_MODE";
MEM_BURST_LEN : INTEGER := 8;
CMD_PATTERN : STRING := "CGEN_ALL";
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00000fff";
ADDR_WIDTH : INTEGER := 30;
DWIDTH : INTEGER := 32;
CMD_SEED_VALUE : std_logic_vector(31 downto 0) := X"12345678";
DATA_SEED_VALUE : std_logic_vector(31 downto 0) := X"ca345675";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
PORT_MODE : STRING := "BI_MODE";
EYE_TEST : STRING := "FALSE"

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Advisor eilert
Advisor
8,440 Views
Registered: ‎08-14-2007

Re: questions about Traffic Generator in MIG

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Hi,

these constants seem to controll the behavior of the traffic generator.

Wether it is necessary or useful to change these settings I can not say, since I don't know anything about your design, tool setup or simulation results.

 

Have a nice simulation

   Eilert

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Explorer
Explorer
8,439 Views
Registered: ‎12-01-2010

Re: questions about Traffic Generator in MIG

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Hi, let's discuss another question. I have successfully added the traffic generator as a stimulus and simulated the waveform of DDR3 SDRAM with Modelsim. Do you think the project can be programmed safely into the FPGA and the traffic generator can give stimulus as simulating?

I know a little about IP CORE and I am not sure if the test bench can work in real board. Since the V-6 board is available in few days later, I'd better to make sure that traffic generator will generate data automatically to the DDR3.

 

Thanks in advance.

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Advisor eilert
Advisor
10,558 Views
Registered: ‎08-14-2007

Re: questions about Traffic Generator in MIG

Jump to solution

Hi,

if I correctly understood the user guide document the testbench is synthesizable as well.

A rare thing, but in this case it makes sense, since a DDR3 interface needs to be verified (and sometimes slightly adjusted) by measurements. 

 

But this can easily be answered if you provide a correct UCF file for the IOBs LOC constraints and simply start an implementation flow. If that runs without errors you just have to wait for your board.

 

Have a nice synthesis

 

  Eilert

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Explorer
Explorer
8,431 Views
Registered: ‎12-01-2010

Re: questions about Traffic Generator in MIG

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In the RTL viewer, the traffic generator is involved. I hope it'll work.

Thanks for your help.

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Explorer
Explorer
7,652 Views
Registered: ‎01-29-2014

Re: questions about Traffic Generator in MIG

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How did you add traffic generator to your design? 

 

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Xilinx Employee
Xilinx Employee
7,645 Views
Registered: ‎02-06-2013

Re: questions about Traffic Generator in MIG

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Hi

 

The example design top level file includes traffic generator modules and this module can be controlled using top level

parameters present in the example_top file.

 

 

Please refer UG406 from below link for more details on  how to control the traffic generator and various test patterns provided with it and the example_top file in the example design shows you how to integrate with your design..

 

http://www.xilinx.com/support/documentation/ip_documentation/ug406.pdf

Regards,

Satish

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