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Explorer
Explorer
3,634 Views
Registered: ‎08-23-2011

questions regarding ISE 14.1 power report ...

hi all xilinx/power estimate gurus,

 

i am using xilinx ISE 14.1 and i ran a design which went through implementation properly (virtex 6 device), no errors, all constraints met.

 

in the design i have a 74MHz i/p clock going into a PLL which generates 74M, 148 and 592MHz o/p clocks. The design is completely routed and I put the constraint in the ucf file to constraint the i/p clock to 74M.

 

QUESTIONS -

 

1) Now, when I run the power analyzer, i see a message saying - user provided less than 75% of clocks, provide missing clock activity in constraint file. i am not sure how to do that as i've already constrained the i/p clock in the ucf already. do i have to add some other constraint too?

 

2) for power estimates, how can i change the activity factor, the supply voltage, the junction and the ambient temperature? 

 

3) also, in the power supply summary i see several power sources, such as vccint, vccaux, vcco25, mgtavcc, mgtavtt. what do these stand for and can i vary the values shown in the power report or are they fixed?

 

4) what does quiscent power mean in the report?

 

5) should i be concerned about the confidence level section of the report, esp where it says low confidence level for the clock nodes activity and I/O nodes activit? how can i bring up the confidence level?

 

thanks in advancne for your inputs ...

 

regards,

Z.

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3 Replies
Xilinx Employee
Xilinx Employee
3,630 Views
Registered: ‎02-16-2014

Re: questions regarding ISE 14.1 power report ...

Hi,

 

Check this user guide pgeno:17 power analysis using Xpower analyzer,

http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug733.pdf

 

Regarding your 4th question,

 

Quiescent power (also called static power) is the power drawn by the device when it is powered up, configured with user logic and there is no switching activity. In XPower Analyzer, the value reported for Total Quiescent Power is composed of these quiescent power components:

  • Device static power – This represents power consumed by the device when it is powered up without programming the user logic. The main contributor to this number is the junction temperature. Any change affecting the device operating environment will affect this power. This power is also called device leakage power.
  • Design static power – This represents the power consumed by the user logic when the device is programmed and without any switching activity. For instance, depending on the device family and resource configuration, some blocks used in a design (such as clock management, I/Os, and Multi-Gigabit Transceivers) will consume a set amount of power regardless of activity.
 
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Xilinx Employee
Xilinx Employee
3,585 Views
Registered: ‎02-16-2014

Re: questions regarding ISE 14.1 power report ...

Hi @zubin_kumar31 

 

Did you get a chance to look at the userguide pointed?

Feel free to post if you have any further queries.

 

 

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Explorer
Explorer
3,552 Views
Registered: ‎08-23-2011

Re: questions regarding ISE 14.1 power report ...

hi,

 

ya ... the user guide helped .. 

 

thanks!

 

z.

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