09-22-2014 10:59 PM
hi all xilinx/power estimate gurus,
i am using xilinx ISE 14.1 and i ran a design which went through implementation properly (virtex 6 device), no errors, all constraints met.
in the design i have a 74MHz i/p clock going into a PLL which generates 74M, 148 and 592MHz o/p clocks. The design is completely routed and I put the constraint in the ucf file to constraint the i/p clock to 74M.
1) Now, when I run the power analyzer, i see a message saying - user provided less than 75% of clocks, provide missing clock activity in constraint file. i am not sure how to do that as i've already constrained the i/p clock in the ucf already. do i have to add some other constraint too?
2) for power estimates, how can i change the activity factor, the supply voltage, the junction and the ambient temperature?
3) also, in the power supply summary i see several power sources, such as vccint, vccaux, vcco25, mgtavcc, mgtavtt. what do these stand for and can i vary the values shown in the power report or are they fixed?
4) what does quiscent power mean in the report?
5) should i be concerned about the confidence level section of the report, esp where it says low confidence level for the clock nodes activity and I/O nodes activit? how can i bring up the confidence level?
thanks in advancne for your inputs ...
09-22-2014 11:12 PM - edited 09-22-2014 11:19 PM
Check this user guide pgeno:17 power analysis using Xpower analyzer,
Regarding your 4th question,
Quiescent power (also called static power) is the power drawn by the device when it is powered up, configured with user logic and there is no switching activity. In XPower Analyzer, the value reported for Total Quiescent Power is composed of these quiescent power components:
09-24-2014 10:43 PM