03-24-2014 06:13 PM
i have 2 custom FPGA boards. the master FPGA has a 100MHz osc that is used as the referenence clock. this goes into a DCM on the master FPGA chip for all the clocking operations. The same clock is buffered and driven out of the master board and sent into a similar FPGA board (slave board). im using regular wires to take the clock from master to slave.
by the time the master's clock reaches the slave, there is a skew of 5 ns between the master's clock o/p and the slave's clock i/p.
is there any on chip primitive/resource/ip core i can use to remove such a skew (inter FPGA clock skew)??? what other methods could i apply to remove the 5 ns skew (apart from trying to shorten the wire lengths)???
please let me know ..
03-25-2014 12:35 PM
03-25-2014 09:20 PM
Suggestion: use the PCI bus approach to clock distribution. The clock generator provides a copy of the bus clock for everyone, including the master. The clock generator's outputs are (by construction) perfectly phase aligned. The transmission paths from the generator to each of the slaves (and masters) are constructed to be equal length, and so each 'party' on the PCI bus receives a clock which is phase aligned with all the other PCI bus 'parties'.
This means that your FPGA acting as 'master' (AND as clock generator) generates two identically timed output copies of the clock. One copy goes to the slave FPGA, and the other copy is returned to the master FPGA. The two clock interconnects are constructed to be identical in length and construction, so the interconnect does not contribute to skew between the two clocks.
Does this make sense?
-- Bob Elkind