Showing results for 
Show  only  | Search instead for 
Did you mean: 
Registered: ‎08-23-2011

reg: board to board FPGA clock deskew ...

hi ... 


i have 2 custom FPGA boards. the master FPGA has a 100MHz osc that is used as the referenence clock. this goes into a DCM on the master FPGA chip for all the clocking operations. The same clock is buffered and driven out of the master board and sent into a similar FPGA board (slave board). im using regular wires to take the clock from master to slave.


by the time the master's clock reaches the slave, there is a skew of 5 ns between the master's clock o/p and the slave's clock i/p.


is there any on chip primitive/resource/ip core i can use to remove such a skew (inter FPGA clock skew)??? what other methods could i apply to remove the 5 ns skew (apart from trying to shorten the wire lengths)???


please let me know ..



0 Kudos
2 Replies
Registered: ‎03-31-2012

So this 5ns is measured from the source FPGA pin to target FPGA pin? This suggests more than 3 feet separation on a regular PCB trace.

Anyway, you can delay the clock into the first fpga by IDELAY and give the second FPGA without delay; this would help you balance the skew.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos
Registered: ‎07-21-2009

Suggestion:  use the PCI bus approach to clock distribution.  The clock generator provides a copy of the bus clock for everyone, including the master.  The clock generator's outputs are (by construction) perfectly phase aligned.  The transmission paths from the generator to each of the slaves (and masters) are constructed to be equal length, and so each 'party' on the PCI bus receives a clock which is phase aligned with all the other PCI bus 'parties'.


This means that your FPGA acting as 'master' (AND as clock generator) generates two identically timed output copies of the clock.  One copy goes to the slave FPGA, and the other copy is returned to the master FPGA.  The two clock interconnects are constructed to be identical in length and construction, so the interconnect does not contribute to skew between the two clocks.


Does this make sense?


-- Bob Elkind

README for newbies is here:

1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos