11-01-2016 12:15 AM
hi, i had a question regarding the the following code snippet -
imy module takes indatawidth and inchannelwidth as parameters while portmapping. and temp_val, temp_data are regs of width depending on the parameters. i assign values to the regs as follows -
if (inchannelwidth < indatawidht - 4)
temp_val[indatawidth-1:inchannelwidth] <= temp_data[indatawidht-1:inchannelwidth];
the above snippet works if the inchannelwidth < indatawidth.
HOWEVER, the above logic fails (while compiling in modelsim), if the inchannelwidth > inchannelwidth. even though there is the if condition, the simulator still compiles the code and errors out. error message says the reg indexes are reversed. (because now inchannelwidth > indatawidht).
so my question is - while dealing with such dynamic parameters, what is the best coding practice to write code/logic so that such the simulators/compilers dont error for different parameter conditions.
do let me know ...
11-01-2016 12:37 AM - edited 11-01-2016 12:37 AM
11-01-2016 01:58 PM - edited 11-01-2016 01:58 PM
Some further suggestions.
When coding your module with parameters, please DOCUMENT the acceptable range for you parameter in the header.
module gizmo #( parameter FOO = 32, // Min 1, no max parameter BAR = 3, // Min 0, Max 3 parameter BAZ = 64 // Only 64 currently supported
parameter QUX = 16 // Min 8, powers of two only )();
Your module may only be used in one configuration, but by at least THINKING about the range of acceptable parameters, it'll help how you code the logic. And this documented range will be greatly appreciated by the next person. (More often than not, that next person is myself sometime down the road...)