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Explorer
Explorer
5,497 Views
Registered: ‎08-23-2011

reg: map report - blocks/signals optimized while porting from virtex6 to virtex4 ...

hi,

 

i have a design which i ported on a virtex6 FPGA (xc6vlx240t) which has 6 i/p LUTs.

the lut utilization in the implemented design summary was about 10875 (7% utlization)

in the map report, i see - 

8 block(s) removed
2 block(s) optimized away
8 signal(s) removed

 

i port the same design on a virtex4 FPGA (xc4vlx200) which has 4 i/p LUTs

the lut utilization in the implemented design summary was about 16222 (9% utilization)

in the map report, i see -

24 block(s) removed

368 block(s) optimized away

64 signal(s) removed

 

im using xilinx ise 14.1

 

i was wondering why, while porting from virtex6 to virtex4, there is such a large change in the blocks being being optimized/removed in the map reports?

 

any clues/ideas?

 

z.

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1 Reply
Explorer
Explorer
5,485 Views
Registered: ‎08-23-2011

Re: reg: map report - blocks/signals optimized while porting from virtex6 to virtex4 ...

moving to xilinx implementation thread ...

 

z.