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Observer zubinkumar
Observer
20,515 Views
Registered: ‎11-23-2010

reg: register to wire mapping in verilog

hi,

 

this is pbbly a very basic question, but i was wondering it there is a syntactically correct AND synthesizable way of mapping a register to a wire in verilog?

 

i know how to map wire to wire (using assign), wire to reg (in always block) and reg to reg (in an always block). and i know under what circumstances you would want to do the above. but is there a way to map reg to wire? and if so, under what circumstrances would you use a reg to wire mapping?

 

thanks in advance ...

 

z.

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3 Replies
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Guide avrumw
Guide
20,510 Views
Registered: ‎01-23-2009

Re: reg: register to wire mapping in verilog

I think you are over-complicating things...

 

The difference between a reg and a wire is purely in how they are given a value:

   - a wire is given a value through a continuous assign or a port connection

   - a reg is given a value through a procedural assign (blocking or non-blocking)

 

Regardless of what kind of thing they are (reg or wire) their value is just a value, and can be used anywhere a value is expected - in a continous assign, as an input port to a module, in a procedural block, in a function or task, etc...

 

So

 

assign my_wire = my_reg;

 

is perfectly valid.

 

But, what are you trying to figure out? The wire and reg are just Verilog constructs. You can use these in ways that they describe hardware, and, when used this way, they can be synthesized into real hardware. But they are not hardware things unto themselves. Most importantly (and a common misconception among beginners) a Verilog register does not necessarily imply a flip-flop.

 

Avrum

 

 

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Observer zubinkumar
Observer
20,504 Views
Registered: ‎11-23-2010

Re: reg: register to wire mapping in verilog

hi, 

 

thanks for the explanation. i usually restrict myself to using regs for o/p ports and for sequential logic and wires for port mapping.

 

i have been trying what you said - assign my_wire = my_reg. i finally got it to work (sim and synth). the mistake i was making was that i was initializing the wire and then assigning the reg to it which was leading to X in the sims.

 

just 2 more questions though ...

 

while doing a reg to reg map, i encountered 2 cases -

 

case1 ...
always @ (clk)
temp2 = temp1;

> this gives the temp1 value on temp2 in the same clk cycle in sims

 

case2 ...
always @ (posedge clk)
assign temp2 = temp1;

> this gives the temp1 value on temp2 after 1 clk cycle delay in sims

 

both cases synth properly. but if i use assign in case2, then i have to put posedge in the always block else the code won't synthesize!

 

my questions -

1) why is there a dependency on posedge and assign in case2?

2) why is there a 1 clk cycle delay in o/p with assign in case2 but not in case1?

 

really appreciate it.

 

z.

 

 

 

 

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Historian
Historian
20,495 Views
Registered: ‎02-25-2008

Re: reg: register to wire mapping in verilog


@zubinkumar wrote:

hi, 

while doing a reg to reg map, i encountered 2 cases -

case1 ...

 

@always @ (clk)

    temp2 = temp1;

 

this gives the temp1 value on temp2 in the same clk cycle in sims


The above is a combinatorial assignment, since it's not sensitive to a clock edge. Of course, the sensitivity list is incomplete so the resulting hardware will not match the simulation. Consider what should happen in simulation if temp1 changes. It should result in an immediate change in temp2, but since the sensitivity list does not include temp1, that assignment won't occur until clk changes (to any state).


case2 ...

 

@always @ (posedge clk)

    assign temp2 = temp1;

 

this gives the temp1 value on temp2 after 1 clk cycle delay in sims


 This also depends on the timing of changes in temp1.


both cases synth properly. but if i use assign in case2, then i have to put posedge in the always block else the code won't synthesize!


You need the posedge to indicate that you want a synchronous result, i.e., a flip-flop. 

 

ALSO: you should ALWAYS use non-blocking assignments in synchronous always blocks, e.g.,

 

@always @(posedge clk)

    temp2 <= temp;

 

There is a lot of information out there about the difference between blocking and non-blocking assignments. Go read.

----------------------------Yes, I do this for a living.