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Explorer
Explorer
7,895 Views
Registered: ‎08-23-2011

reg: timing issue and planahead ...

hi,

 

i have a design where inside a particular module (sub1), i have timing violation because of too many logic levels.

 

in the ise 14.1 timing report, the path comes out as -

 

start point with worst case slack - top/m0/maincontroller/sub1/module1/controller/linkspeed[1]

end point with worst case slack - top/m0/maincontroller/sub1/module2/recv/st0[7]

levels of logic = 19

slack = -2.45ns

 

since the timing issue is in a path which starts and ends inside the sub1 module, so is it correct to assume that no matter where we manually place or how we manually resize the sub1 module (using xilinx planahead), since the  violation is still inside sub1, we will still have the same violations. is my understanding correct?

 

can manually placing or manually resizing module1 and module2 (by declaring them as pblocks) help in reducing the slack and coming closer to the timing at least? is this the general approach?

 

what other tricks can be tried in planahead to reduce the slack? I have already tried over/under constraining the timing of my design without much help.

 

at what point should logic be investigated so that we can reduce the logic level?

 

help! :)

 

z.

 

 

 

 

 

 

 

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Professor
Professor
7,876 Views
Registered: ‎08-14-2007

You have to look at the detailed path description in the Static Timing report.  This will tell you how much of the path is due to routing vs logic.  If more than about 60% of the path is routing delay, you can probably reduce the path with a better placement.  The fact that the path is within a module does not mean that the components in the path are necessarily placed near eachother.  On the other hand 19 levels of logic is a lot, especially if they are not carry-chain levels.

-- Gabor
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