UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
12,945 Views
Registered: ‎05-11-2010

regarding sensitivity list in vhdl process

I have read in a vhdl book that if the sensitivity list in vhdl process is left blank the process executes indefinitely but if i leave the sensitivity list blank, the xilinx synthesize tool shows error.So i put a dummy input bit signal in the sensitivity list and as far as i know the process executes only when there is a event on the sensitivity list.But in modelsim it takes by default the value as 0 for this bit signal and then even if dont change it's value the simulation works correct and process executes.


How is this possible ?

0 Kudos
3 Replies
Historian
Historian
12,904 Views
Registered: ‎02-25-2008

Re: regarding sensitivity list in vhdl process

 


@gopalkrishnarn wrote:

I have read in a vhdl book that if the sensitivity list in vhdl process is left blank the process executes indefinitely but if i leave the sensitivity list blank, the xilinx synthesize tool shows error.So i put a dummy input bit signal in the sensitivity list and as far as i know the process executes only when there is a event on the sensitivity list.But in modelsim it takes by default the value as 0 for this bit signal and then even if dont change it's value the simulation works correct and process executes.


How is this possible ?


 

You are likely seeing errors in processes without a sensitivity list because your code has no logic that "waits" for something to happen.

 

A process that HAS a sensitivity list will only trigger on a change in the signals in that list. For a registered process, the only signal that is of interest is the clock (think about a D flip-flop). For a combinatorial process, you must consider EVERY signal on the right-hand side of all assignments.

 

It is certainly legal to have a process without a sensitivity list. However, this sort of process must have some kind of time-delay or wait mechanism; otherwise the process will try to loop in zero time.

 

Please please please buy a copy of Peter Ashenden's "The Designer's Guide To VHDL." It will clarify all of this for you.

----------------------------Yes, I do this for a living.
0 Kudos
Highlighted
Contributor
Contributor
12,883 Views
Registered: ‎06-12-2009

Re: regarding sensitivity list in vhdl process

A process executes indefinitely anyway.

The error message you saw is probably a warning saying that the synthesizer detected signals missing from the list and is adding them automatically.  I have seen many synthesizers that do this.

Jim

 

0 Kudos
Advisor eilert
Advisor
12,878 Views
Registered: ‎08-14-2007

Re: regarding sensitivity list in vhdl process

Hi, some things to remember about sensitivity lists and processes: - They are only used in simulation and ignored by synthesis, even if some tools give warnings (mostly to tell you that the simulation may be inaccurate) - ALL processes are triggered once at time 0 - Without a sensitivity list a process has to have at least one wait-statement, otherwise it restarts infinitely and your simulator stalls. Post your code, so we can give you more specific information about how it works. Have a nice simulation Eilert
0 Kudos