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Explorer
Explorer
11,037 Views
Registered: ‎08-23-2011

removing hold violation on CDC regs. methods/ucf constraints?

hi,

 

i have a question regarding hold violation during clock domain crossing.

 

i have a design where a reg1 works @ 20MHz and it sends data to reg2 @ 40MHz. I am implementing the design using xilinx ISE 14.1, on a virtex 6 device. i synthesized the design using synplify. the 20M and 40M clocks are generated using a xilinx PLL whose i/p clock is 100M (which I have constrained in the ucf file).

 

when i implement the design (translate/map/PR), translate, map, pass, but PR gives hold violation on the above regs. reg1 being the sournce and reg2 being the destination.

 

Is there any constraint that i can put in the ucf file which would help remove the hold violation on the above regs? 

 

What other strategies can i use to remove hold violations on such CDC regs?

 

Please let me know ...

 

thanks.

z.

 

 

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23 Replies
Teacher eteam00
Teacher
11,029 Views
Registered: ‎07-21-2009

Re: removing hold violation on CDC regs. methods/ucf constraints?

A critical question is whether the two clocks are derived from a common timebase (and if yes, how the two clocks are generated and buffered).

Is this an async interface (the clock domain crossing) or is this a matter of two isochronous clock domain with excessive skew?

 

-- Bob Elkind

SIGNATURE:
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Summary:
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3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Historian
Historian
11,019 Views
Registered: ‎01-23-2009

Re: removing hold violation on CDC regs. methods/ucf constraints?

The real question is "why is there a hold violation on this path"?

 

Clocks with "reasonable" ratios coming from the same PLL can be treated as synchronous. This means that you can cross between them with "normal" paths. With a 20MHz and 40MHz clock, these should end up with a 25ns requirement. There should be no particular issue with the hold checks; there will be a bit more clock skew (due to the PLL output phase error), but the tools should easily be able to fix that.

 

So, why are you seeing hold failures? My guess is that there is something wrong with the clock buffers (or something else about the construction of the clock generator). If the two clocks come out of the same PLL and use the same kind of buffers then there shouldn't be a hold time failure. But, if either of these two conditions is not true, then the two clocks do not remain in phase, and then you may not be able to cross them synchronously.

 

If you do need to cross them asynchronously, then you will need an appropriate clock crossing circuit on the paths, and then you will need a timing exception. In ISE it is a normally a TIG or a FROM/TO with DATAPATHONLY.

 

Avrum

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Explorer
Explorer
10,998 Views
Registered: ‎08-23-2011

Re: removing hold violation on CDC regs. methods/ucf constraints?

hi bob,

 

thanks for the reply. the 20M and 40M clocks come from the same source - a pll whose i/p clock is 100M. so would i need to issue some form or TIG or some other constraint in the UCF file?

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Explorer
Explorer
10,996 Views
Registered: ‎08-23-2011

Re: removing hold violation on CDC regs. methods/ucf constraints?

hi avrum, 

 

as mentioned in my reply to bob - the clocks come out of the same pll, whose i/p clock is 100M (which i constrained).

 

since the 20M signal and 40M signal may go through their own set of buffers/wires to the source and destination, is it possible that a difference in the no. of buffers/wires on the 20M path to the source reg (reg1) and the no. of buffers/wires on the 40M path on the destination reg (reg2) could be causing the hold violation?

 

would removing some of the buffers/wires help in resolving this?

 

Or would one have to look into the code indepth and add combinational logic to the faulty paths because its always suggested that is the best way to remove this issue. if so, what comb. delay should be added? should i add some logic function, some mathematical function on either the source or dest reg? 

 

do let me know ,,,

 

thanks and regards,

z.

 

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Teacher eteam00
Teacher
10,982 Views
Registered: ‎07-21-2009

Re: removing hold violation on CDC regs. methods/ucf constraints?

... the clocks come out of the same pll, whose i/p clock is 100M (which i constrained).

 

You might want to consider distributing the 40MHz clock, plus a generated 20MHz clock enable, to the logic which clocks at 20MHz. This consolidates the two clock domains into a single clock domain.

 

since the 20M signal and 40M signal may go through their own set of buffers/wires to the source and destination,

 

They must go through their own set of buffers.

 

... is it possible that a difference in the no. of buffers/wires on the 20M path to the source reg (reg1) and the no. of buffers/wires on the 40M path on the destination reg (reg2) could be causing the hold violation?

 

If the clocks are properly buffered, the answer to this question is no.

 

would removing some of the buffers/wires help in resolving this?

 

You need a better understanding of on-chip clock distribution.  The Xilinx FPGA on-chip clock buffers ensure that (in the context of your design) clock skew (and clock skew between the two 20M/40M clock domains) within the FPGA fabric is practically zero.

 

Or would one have to look into the code indepth and add combinational logic to the faulty paths because its always suggested that is the best way to remove this issue. if so, what comb. delay should be added? should i add some logic function, some mathematical function on either the source or dest reg?

 

You are applying measures which are entirely appropriate for ASICs to an FPGA design.  In the context of FPGA, these measures are both unnecessary and problematic.  Xilinx has developed and incorporated into their PLLs and clock buffers a level of consistency which makes such skew-management countermeasures unnecessary.  The question remains: how are you distributing/buffering the 20M and 40M clocks in your design?

 

Avrum's previous response in this thread is absolutely correct.  If you use the available dedicated-purpose clock buffers, which drive dedicated-purpose clock distribution interconnect networks, the skew between the 20M and 40M clock domains originating from the same PLL should be (for all practical purposes) zero.  By "practically zero", it is meant that the total clock skew (plus maximum required register data input hold time) is guaranteed (by design) less than the minimum register clock to data output time (plus minimum register output to register input interconnect delay).

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Historian
Historian
10,967 Views
Registered: ‎01-23-2009

Re: removing hold violation on CDC regs. methods/ucf constraints?

To be clear, the two output clocks of the PLL must go through identical buffers; either each uses one BUFG or each uses one BUFH. No other buffers or logic should be used on the clock path - the output of the buffers should go directly to the clock pin inputs of all flip-flops on the respective domains.

 

There are some minor variations, depending on what exactly you want to do (the BUFG and BUFH have some other capabilities), but the key is that the clock distribution mechanisms in FPGA are already implemented on the die - you have to target your design to these clock networks. FPGAs are not ASICs; in ASICs, there are lots of fancy things you can do on clock trees (gating, division, etc...). In FPGAs, there are specific mechanisms for doing this using the existing clock resources, and these are really the only (reasonable) way of performing these tasks.

 

Tell us exactly what you want to do, and exactly what clocking resources you are using. You can also post the failing path.

 

Avrum

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Explorer
Explorer
10,944 Views
Registered: ‎05-03-2012

Re: removing hold violation on CDC regs. methods/ucf constraints?

Timing report should contain details which can help you with holds.

You can check with PlanAhead why you data path is so short and why it could not be longer.

Also there you can check clock connectivity and verify that all clocks are going thrue BUFG.

At finish you can check Jitter and Phase Error in clock report.

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Explorer
Explorer
10,942 Views
Registered: ‎05-03-2012

Re: removing hold violation on CDC regs. methods/ucf constraints?

If you dont need cross clock domain verification at all please read

http://www.xilinx.com/support/answers/34348.htm

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Teacher muzaffer
Teacher
10,891 Views
Registered: ‎03-31-2012

Re: removing hold violation on CDC regs. methods/ucf constraints?

So the 20M and 40M clocks are coming from the same PLL? In that case the hold violations should be happening because of excessive skew at the output of pll through different clock paths. You can probably help this with some placement constraints. When the clocks of two registers can be traced to the same root clock, they are not considered clock domain crossing.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Explorer
Explorer
9,306 Views
Registered: ‎08-23-2011

Re: removing hold violation on CDC regs. methods/ucf constraints?

hi all,

 

been trying to figure this one out ...

 

here is a report of the failing path - 

 

as mentioned before - i/p clk to PLL = 100M, o/p clk = 20 and 80M (changed from 40M) from the same pll ... still giving hold violations ...

 

please let me knwo which strategy i should apply or where i can analyse the code and add buffers/make changes to the ucf constraints to resolve this ... any thing to go on would be great at this point ...

 

regards,

z.

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Teacher eteam00
Teacher
9,303 Views
Registered: ‎07-21-2009

Re: removing hold violation on CDC regs. methods/ucf constraints?

Which of the several bits of advice offered in this thread have already been tried or applied?  Which have not yet been tried?  Have the results varied?

 

Also, a number of useful details have been requested, do you have time to answer some of these questions?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Explorer
Explorer
9,289 Views
Registered: ‎08-23-2011

Re: removing hold violation on CDC regs. methods/ucf constraints?

my bad, my sincerest apologies :)

 

i forgot to copy paste the timing report for the failing path in my previous post 

 

as mentioned before - i changed the PLL o/p from 40M to 80M

 

so now the i/p to PLL is 100M (constrained in ucf), o/p of PLL is 20M and 80M (from the previous posts, i gather that these are derived clocks from the same PLL so no constraints are needed on the 20M and 80M clock o/p) ... still it fails.

I added some combo logic to some of the sr-dest paths that seem to fail but no luck.

at this point im tracing where all the 20M and 80M clock paths go .. would it be a concern if the 20M clock was being routed to more sub-modules as compared to 80M clock? Would that effect the failures?

 

any other places i can look into the code and make changes and/or constrants in the ucf file for the path below?

 

timing report for a failing path is as follows -

Slack (hold path): -0.230ns (requirement - (clock path skew + uncertainty - data path))
Source: toshiba_top/bky_reg/r_vsc_vcy13[7] (FF)
Destination: toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/VSCALER/YL0_coff/r_coff[7] (FF)
Requirement: 0.000ns
Data Path Delay: 0.144ns (Levels of Logic = 1)
Clock Path Skew: 0.093ns (1.521 - 1.428)
Source Clock: clkgenout[0] rising at 0.000ns
Destination Clock: clkgenout[2] rising at 0.000ns
Clock Uncertainty: 0.281ns

Clock Uncertainty: 0.281ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.315ns
Phase Error (PE): 0.120ns

Minimum Data Path at Fast Process Corner: toshiba_top/bky_reg/r_vsc_vcy13[7] to toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/VSCALER/YL0_coff/r_coff[7]
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X58Y55.DQ Tcko 0.098 toshiba_top/vsc_vcy13[7]
toshiba_top/bky_reg/r_vsc_vcy13[7]
SLICE_X59Y55.B6 net (fanout=3) 0.048 toshiba_top/vsc_vcy13[7]
SLICE_X59Y55.CLK Tah (-Th) 0.002 toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/VSCALER/VCY_L0[7]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/VSCALER/YL0_coff/r_coff_18_10[7]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/VSCALER/YL0_coff/r_coff_18_15mux_RNO_0[7]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/VSCALER/YL0_coff/r_coff_18_15mux[7]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/VSCALER/YL0_coff/r_coff[7]
------------------------------------------------- ---------------------------
Total 0.144ns (0.096ns logic, 0.048ns route)
(66.7% logic, 33.3% route)

--------------------------------------------------------------------------------

Paths for end point toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP1_coff/r_coff[2] (SLICE_X38Y53.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path): -0.071ns (requirement - (clock path skew + uncertainty - data path))
Source: toshiba_top/bky_reg/r_vsc_hcy9[2] (FF)
Destination: toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP1_coff/r_coff[2] (FF)
Requirement: 0.000ns
Data Path Delay: 0.309ns (Levels of Logic = 1)
Clock Path Skew: 0.099ns (1.479 - 1.380)
Source Clock: clkgenout[0] rising at 0.000ns
Destination Clock: clkgenout[2] rising at 0.000ns
Clock Uncertainty: 0.281ns

Clock Uncertainty: 0.281ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.315ns
Phase Error (PE): 0.120ns

Minimum Data Path at Fast Process Corner: toshiba_top/bky_reg/r_vsc_hcy9[2] to toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP1_coff/r_coff[2]
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X36Y56.CQ Tcko 0.115 toshiba_top/vsc_hcy9[3]
toshiba_top/bky_reg/r_vsc_hcy9[2]
SLICE_X38Y53.A6 net (fanout=3) 0.217 toshiba_top/vsc_hcy9[2]
SLICE_X38Y53.CLK Tah (-Th) 0.023 toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/HCY_P1[2]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP1_coff/r_coff_18_13[2]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP1_coff/r_coff_18_15mux_RNO_0[2]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP1_coff/r_coff_18_15mux[2]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP1_coff/r_coff[2]
------------------------------------------------- ---------------------------
Total 0.309ns (0.092ns logic, 0.217ns route)
(29.8% logic, 70.2% route)

--------------------------------------------------------------------------------

Paths for end point toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP0_coff/r_coff[2] (SLICE_X39Y53.B5), 1 path
--------------------------------------------------------------------------------
Slack (hold path): -0.013ns (requirement - (clock path skew + uncertainty - data path))
Source: toshiba_top/bky_reg/r_vsc_hcy1[2] (FF)
Destination: toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP0_coff/r_coff[2] (FF)
Requirement: 0.000ns
Data Path Delay: 0.358ns (Levels of Logic = 1)
Clock Path Skew: 0.090ns (1.479 - 1.389)
Source Clock: clkgenout[0] rising at 0.000ns
Destination Clock: clkgenout[2] rising at 0.000ns
Clock Uncertainty: 0.281ns

Clock Uncertainty: 0.281ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.315ns
Phase Error (PE): 0.120ns

Minimum Data Path at Fast Process Corner: toshiba_top/bky_reg/r_vsc_hcy1[2] to toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP0_coff/r_coff[2]
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X41Y58.CQ Tcko 0.098 toshiba_top/vsc_hcy1[3]
toshiba_top/bky_reg/r_vsc_hcy1[2]
SLICE_X39Y53.B5 net (fanout=3) 0.262 toshiba_top/vsc_hcy1[2]
SLICE_X39Y53.CLK Tah (-Th) 0.002 toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/HCY_P0[2]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP0_coff/r_coff_18_10[2]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP0_coff/r_coff_18_15mux_RNO_0[2]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP0_coff/r_coff_18_15mux[2]
toshiba_top/vou_top/vou_vf0/scaler_top/bky_scaler/HSCALER/YP0_coff/r_coff[2]
------------------------------------------------- ---------------------------
Total 0.358ns (0.096ns logic, 0.262ns route)
(26.8% logic, 73.2% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_TABULA_clkgen_V0_clkout2 = PERIOD TIMEGRP "TABULA_clkgen_V0_clkout2"
TS_clkref_p / 0.8 HIGH 50%;

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Explorer
Explorer
9,280 Views
Registered: ‎08-23-2011

Re: removing hold violation on CDC regs. methods/ucf constraints?

also ... 

 

i further analyzed the code and there is a place where the 20M clock is being inverted by using the ~ in verilog. 

 

so would this force the 20M clock out of the dedicated FPGA clock route and onto some combo logic fabric thereby adding to the hold violation?

 

 

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Teacher muzaffer
Teacher
9,278 Views
Registered: ‎03-31-2012

Re: removing hold violation on CDC regs. methods/ucf constraints?

Your clock skew is only 98 ps so that would help much to solve the hold. Your best bet is to insert some buffers to solve this issue. It is interesting that par is not doing it for you.
What does the slow path look like for these registers (ie source and destination). Especially on the destination if you have setup slack, you can add a buffer (or two) with keep attribute and see if that helps.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Teacher muzaffer
Teacher
9,276 Views
Registered: ‎03-31-2012

Re: removing hold violation on CDC regs. methods/ucf constraints?

your report says:
Source Clock: clkgenout[0] rising at 0.000ns
Destination Clock: clkgenout[2] rising at 0.000ns

so both clocks are rising edge. 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Explorer
Explorer
9,271 Views
Registered: ‎08-23-2011

Re: removing hold violation on CDC regs. methods/ucf constraints?

hi muzaffer,

 

here's what im trying -

 

as mentioned in the prev post - the 20M clock going into one of the sub-modules (DIFFERENT FROM THE MODULE MENTIONED ABOVE) of the design was being inverted using the ~ operator.

 

so ive removed that operator and am trying to synt. and implement the design again. but would it be correct in assuming that the ~ operator on the clock would move the clock away from the dedicated clock route and onto some combinational logic rounte, thus increasing such issues?

 

also, should i add the BUFG just on the o/p of the pll on the 80M clock? or should i also add this buffer on the 20M clock as well? or shoudl it be placed before the 20M or 80M clock enters the sub-module which is giving the violation? which would be the best place to but the buffers and how many appx? (i'll ensure i put the keep attribute)

 

lastly - if the 20M clock is being routed to 4 sub-modules and the 80M clock is being routed to ... say 10 or 11 modules, would this impact the hold violations (based on some fanout issue), or such things are taken care of by the tool itself?

 

z.

 

 

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Teacher eteam00
Teacher
9,267 Views
Registered: ‎07-21-2009

Re: removing hold violation on CDC regs. methods/ucf constraints?

i further analyzed the code and there is a place where the 20M clock is being inverted by using the ~ in verilog. 

 

so would this force the 20M clock out of the dedicated FPGA clock route and onto some combo logic fabric thereby adding to the hold violation?

 

The inversion is accomplished inside the CLB, there is no additional combinatorial logic inserted in the clock path.  Having said that, there is additional clock skew introduced in that it cannot be assumed that rising clock transition delays through the clock buffer and distribution are identical to falling clock transition delays.

 

Here is something worth trying, with the assumption that 20M and 80M rising clock edges are coincident:

 

// 80m to 20M

reg  data80M, data80Mdelay;  // 80M domain source data reg followed by 80M reg delayed by 1/2 clock cycle

reg data20M;  // destination 20M data register

 

always @(posedge clk80M) data80M <= <data>;  // replace <data> with actual source data

always @(negedge clk80M) data80Mdelay  <= data80M;  // delay the data by half clock cycle

always @(posedge clk20M) data20M <= data80Mdelay;  // there should be no hold time problems

 

and in the opposite direction

 

// 20m to 80M

reg  data80M, data80Mdelay;  // 80M domain dest data reg preceded by 80M reg delayed by 1/2 clock cycle

reg data20M;  // source 20M data register

 

always @(posedge clk20M) data20M <= <data>;  // replace <data> with actual source data

always @(negedge clk80M) data80Mdelay  <= data20M;  // delay the data by half clock cycle

always @(posedge clk80M) data80M <= data80Mdelay;  // there should be no hold time problems

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Explorer
Explorer
9,257 Views
Registered: ‎08-23-2011

Re: removing hold violation on CDC regs. methods/ucf constraints?

hi bob,

 

will try what you mentioned - delaying the 80M data by putting it on negedge and then clocking it out on the posedge,  I will also try what muzzafer said - add buffers on the clock.

 

however, regarding the clock inversion using the ~ operator, you said - 

 

there is additional clock skew introduced in that it cannot be assumed that rising clock transition delays through the clock buffer and distribution are identical to falling clock transition delays.

 

so i gather that this could have a bearing on hold issues because skew is bad for hold time? just asking if my interpretation/understanding is correct ...

 

z.

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Teacher eteam00
Teacher
9,251 Views
Registered: ‎07-21-2009

Re: removing hold violation on CDC regs. methods/ucf constraints?

so i gather that this could have a bearing on hold issues because skew is bad for hold time? just asking if my interpretation/understanding is correct ...

 

Depending upon specific implementation details, yes, your understanding is correct.

 

-- Bob Elkind

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Teacher muzaffer
Teacher
7,143 Views
Registered: ‎03-31-2012

Re: removing hold violation on CDC regs. methods/ucf constraints?

>> I will also try what ... said - add buffers on the clock.

That's not what Muzaffer said ;-)


I was not suggesting adding buffers on the clock. In FPGAs messing with the clock tree is not advisable (although the Vivado router seems to try :-). I was suggesting to add buffers to the datapath in the failing hold paths IF there is enough setup slack for the same target register. Basically report timing on the destination register of the failing hold paths and if you have enough setup slack, you can add buffers just at the input of the register.

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Teacher eteam00
Teacher
7,139 Views
Registered: ‎07-21-2009

Re: removing hold violation on CDC regs. methods/ucf constraints?

I was suggesting to add buffers to the datapath in the failing hold paths IF there is enough setup slack for the same target register. Basically report timing on the destination register of the failing hold paths and if you have enough setup slack, you can add buffers just at the input of the register.

 

The two suggestions -- added combinatorial delay buffers between registers or a 1/2 cycle delay register -- are similar  solutions to the same problem.  All else being equal, the 1/2 cycle delay register implementation is likely to be more predictable and avoids the need for coding tricks to prevent 'trimming' in synthesis.

 

-- Bob Elkind

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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Explorer
Explorer
7,117 Views
Registered: ‎08-23-2011

Re: removing hold violation on CDC regs. methods/ucf constraints?

hi,

 

so there was this 20M clock in the design which was being inverted using ~ operator and being used in one of my design's sub- modules. when this was being used and i was implementing the design, the design summary during PAR would show some timing errors and failure to meet constraints. it would show Timing: completed - 6 errors found which would be hold violations/errors.

 

i generated the same clock (with a 180 pahse shift from the PLL) and now the PAR report is clean, the design summary shows all constranits met and no timing errors. 

 

also, when i go to the timing contraints in the design overview, it shows all constraints met (100M i/p clock and all the derived clocks). But when I click on any one of the timing contraints, it takes me to top.twx and there i can still see about 6 hold errors or 6 timing errors on one of the clock paths. 

 

So my questions are - 

1) why is the design summary/PAR report saying no timing errors but the timing report (.twx) is still showing some hold errors? which one should be correct and to be believed? i ensured that the reports are latest by doing a reset report.

 

2) clkout2 of my PLL should be giving 80M, and this is a derived clock. but in the design summary, i see that xilinx automatically generates a constraint for this derived clock and sets it to .8 HIGH 50%. how does the .8 correspond to 80MHz? my i/p clk is 100MHz and is constrained to with 10ns in the ucf file.

 

3) looking at the above, do i need to specify constraints for the derived clocks too?

 

z. 

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Explorer
Explorer
7,064 Views
Registered: ‎08-23-2011

Re: removing hold violation on CDC regs. methods/ucf constraints?

i thought i'd just summarize ....

 

there was a clock which was being inverted and used in one of the sub-modules using ~ operator.

 

when i changed that and generated the same clock from the PLL (180 deg phase shift), i got a timing score of 0 and all constraints met in the design summary, map, par etc. passing and no errors in those reports.

 

so i guess that sorts out the problems for me for now ...

 

however, when i looked into the .twx report, i still saw there were some paths that were showing setup/hold violations. i am not sure why this would happen esp. when implementation is clean, the timing score in the design summary = 0.

 

i know that most of the setup/hold errors show up on source/dest whcih cross clock domains and i read somewhere that if hold issues show up on CDC source-dest, then it can be ignored.

 

but does the same apply for setup?

 

z.

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