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Explorer
Explorer
6,967 Views
Registered: ‎08-23-2011

restrictions on using posedge Vs negedge on xilinx FPGAs ..

hi,

 

i am able to implement my designs using both posedge and negedge. however, is there any restriction that only posedge should be used on FPGAs?

 

i am targetting virtex6 vlx760 devices (ISE14.1).

 

i ask because long back i vaguely remember reading somewhere that "certain FPGAs only support posedge logic". is it true for any older xilinx FPGA family type?

 

any restricstion i need to keep in mind while using the negedge for my logic?

 

help refresh :)

 

z.

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Teacher muzaffer
Teacher
6,959 Views
Registered: ‎03-31-2012

Re: restrictions on using posedge Vs negedge on xilinx FPGAs ..

as long as you don't use them in the same event expression, you are OK. I don't know of any Xilinx FPGAs which only support posedge. One thing you need to pay attention is that a mixed edge system has half the period available for timing so meeting timing would be more difficult.
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