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## General Technical Discussion

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Observer
Posts: 28
Registered: ‎11-11-2016

# rotate right in verilog

Hi. I'm struggling making a 16 right rotating register. For the left rotation it was easy. Right rotating register has a glitch.

```reg [15:0] result;
reg carry;

ROL:
{carry, result} = operand0 << 1'b1;
result[0] = carry;

ROR: WITH PROBLEMS!
{result,carry} = operand0 >> 1'b1;
result = {result,carry};
result[15] = carry;```

Let's assume result = 0x0002. After ROR instr. carry is set to 1, so the result will be 0x8001, instead of 0x0001. I want somehow the carry from {result,carry} concatenation to be outside the result, like a [-1] location similarly to a 17 location from the ROL concatenation. I hope you can understand me. Also, I do not want more than 16 flipflops after code synthesis.

Thanks you!

Accepted Solutions
Scholar
Posts: 2,187
Registered: ‎04-26-2015

## Re: rotate right in verilog

Wouldn't this work?

`result = {operand0[0], operand0[15:1]};`

All Replies
Observer
Posts: 28
Registered: ‎11-11-2016

## Re: rotate right in verilog

I'm interested in a borrow bit similarly to a carry bit.

Scholar
Posts: 2,187
Registered: ‎04-26-2015

## Re: rotate right in verilog

Wouldn't this work?

`result = {operand0[0], operand0[15:1]};`

Observer
Posts: 28
Registered: ‎11-11-2016

## Re: rotate right in verilog

Yes, it works.

Visitor
Posts: 4
Registered: ‎11-13-2017

## Re: rotate right in verilog

Hi everyone. I've written verilog code to display a 1 pixel crosshair on a monitor. But idk how to make it rorate on the screen. I've never learned this before. Verilog is a new language to me. Could someone help me out pls?

module crosshair_1pixel(
input clk,
input rst,
output reg [2:0] color, // output red
output wire HS, // horizontal sink
output wire VS // vertical sink
);

// Define constant as local parameter
// Horizontal display
localparam display_hz = 640; // horizontal display area
localparam total_hz = 800;
localparam sync_pulse_1 = 96;
localparam backporch_end = 144;
localparam frontporch_begin = 784;
localparam backporch_end_a = 463;
localparam frontporch_begin_a = 465;

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Veritcal display
localparam display_vr = 480; // vertical display area
localparam total_vr = 525;
localparam sync_pulse_2 = 2;
localparam backporch_end_1 = 35;
localparam frontporch_begin_2 = 515;
localparam backporch_end_1_a = 274;
localparam frontporch_begin_2_a = 276;

// Creating clk_div
localparam constantNumber = 2;
reg [9:0] count;
reg clk_div;

always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
count <= 10'b0;
else if (count == constantNumber - 1)
count <= 10'b0;
else
count <= count + 1;
end

always @ (posedge(clk), posedge(rst))
begin
if (rst == 1'b1)
clk_div <= 1'b0;
else if (count == constantNumber - 1)
clk_div <= ~clk_div;
else
clk_div <= clk_div;
end

// Creating vetical and horizontal counters
reg [9:0] hzc; //horizontal counter
reg [9:0] vrc; //vertical counter

always @(posedge(clk_div), posedge(rst))
begin
if(rst == 1)
begin
hzc <= 0;
vrc <= 0;
end
else
begin

if(hzc < total_hz - 1) // horizontal counter reset itself when it reaches the end of the line (799 in this case )
hzc <= hzc + 1; // then starts to increment by 1
else
begin
hzc <= 0;
if(vrc < total_vr - 1) // same here for vertical counter
vrc <= vrc + 1; // increment by 1
else
vrc <= 0;
end
end
end

// Creating sync pulses
assign HS = (hzc < sync_pulse_1) ? 1:0;
assign VS = (vrc < sync_pulse_2) ? 1:0;

// Displaying red color
always@(*)
begin

if (((hzc >= backporch_end) && hzc < (frontporch_begin)) && (((vrc >= (backporch_end_1_a)) && (vrc < frontporch_begin_2_a))))
begin
color = 3'b111;
end

else if(((hzc >= backporch_end_a) && hzc < (frontporch_begin_a)) && (((vrc >= (backporch_end_1)) && (vrc < frontporch_begin_2))))
begin
color = 3'b111;
end
else
color = 0;

end
endmodule

Scholar
Posts: 2,187
Registered: ‎04-26-2015

## Re: rotate right in verilog

@tinhle123 You've posted this in two threads now, and neither is relevant!

I would suggest (a) figuring out how you rotate a 1-pixel crosshair in another language (eg. C or Matlab. Python or Java would be fine if you avoid just calling the "rotate" function), then (b) try to implement that in Verilog, and then (c) if that fails, come to the Xilinx forums and start a new thread requesting help with the failure (rather than asking how to begin).

Visitor
Posts: 4
Registered: ‎11-13-2017

## Re: rotate right in verilog

Could you please tell me how to post a new thread. I don't have any ideas how to do that. Thanks
Scholar
Posts: 2,187
Registered: ‎04-26-2015

## Re: rotate right in verilog

Go to an appropriate forum (eg. the Welcome and Join one, here) and click the "New Message" button: