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Adventurer
Adventurer
2,960 Views
Registered: ‎12-16-2010

share SPI pins for bootstrap FLASH and slave interface from uP

Hello.

We want to develop a design employing a Spartan3 FPGA, a SPI FLASH with the bitstream and a microprocessor both controlling the FPGA during operation and accessing the SPI FLASH when needed.

Basically, during startup, the FPGA must access the SPI FLASH as master of the SPI bus, then releasing it on DONE.

At this moment the uP becomes master of SPI, and should be able to communicate with both FPGA and SPI memory, now both behaving as slave.

I think this should be possible, because CCLK, MOSI and DIN of the FPGA can be used as user IO after configuration.

I'm not sure about the CSO_B pin, connected to the CS of the FLASH, because after config it should be controlled by the uP.

Do I need to put some sort of multiplexer on the circuit or there's an easy trick to do it?

There's an adviced circuit schematic to achieve this as example?

Thanks

 

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Instructor
Instructor
2,953 Views
Registered: ‎07-21-2009

Re: share SPI pins for bootstrap FLASH and slave interface from uP

We want to develop a design employing a Spartan3 FPGA, a SPI FLASH with the bitstream and a microprocessor both controlling the FPGA during operation and accessing the SPI FLASH when needed. Basically, during startup, the FPGA must access the SPI FLASH as master of the SPI bus, then releasing it on DONE.

The microprocessor must tri-state its SPI interface until the FPGA is configured.

At this moment the uP becomes master of SPI, and should be able to communicate with both FPGA and SPI memory, now both behaving as slave. I think this should be possible, because CCLK, MOSI and DIN of the FPGA can be used as user IO after configuration.

Correct, the configuration pins you list become user IOs after configuration.

I'm not sure about the CSO_B pin, connected to the CS of the FLASH, because after config it should be controlled by the uP.

The FPGA CSO_B pin also becomes a user IO after configuration.

Do I need to put some sort of multiplexer on the circuit or there's an easy trick to do it?

No multiplexer needed.  There should be a pullup R on the CCLK and CSO_B signals on the board, to avoid problems when neither the FPGA or microprocessor are driving the SPI interface.  See Table 4-8 in UG332.

 

You will need to take care with the routing and termination of the SPI lines, particularly the CCLK (SPI CLK) net.  Ringing or glitches due to reflections on the CCLK signal would be a show-stopper for you, regardless of CCLK (SPI CLK) frequency.  The data lines are susceptible to signal integrity malpractice as well, but slowing SPI CLK frequency can solve data line problems.  If you aren't sure how to ensure proper SPI CLK routing and termination, you should seriously consider SPICE simulation (or equivalent).

 

- Bob Elkind

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