UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Scholar ronnywebers
Scholar
10,719 Views
Registered: ‎10-10-2014

simple VHDL pipeline register

I'm creating a simple pipeline register, to delay a value by 1 clock cycle. I have a basic VHDL question - is there any difference between the following to processes :

 

    signal reg_data_buffer : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0) := (others => '0');     -- 1-word pipeline reg

...
begin

	process(clock)
	begin
	   if rising_edge(clock) then
	       if s00_axis_tvalid = '1' then
                reg_data_buffer <= s00_axis_tdata;
               end if;
	   end if;
	end process;

and this version, with an else clause explicitly stating it has to keep the same value if 's00_axis_tvalid' is not '1'

 

	process(clock)
	begin
	   if rising_edge(clock) then
	       if s00_axis_tvalid = '1' then
                reg_data_buffer <= s00_axis_tdata;
               else
                reg_data_buffer <= reg_data_buffer;
               end if;
	   end if;
	end process;

 

does this synthesize any different?

** kudo if the answer was helpful. Accept as solution if your question is answered **
0 Kudos
10 Replies
Xilinx Employee
Xilinx Employee
10,713 Views
Registered: ‎08-01-2008

Re: simple VHDL pipeline register

the first process may infer transparent latch and send register . I would recommend to synthesis and check schematics . the second process recommends for good coding style
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Scholar ronnywebers
Scholar
10,703 Views
Registered: ‎10-10-2014

Re: simple VHDL pipeline register

thanks @balkris, I tried out both, and checked the schematic after synthesis, they look identical like this :

 

pipeline reg.png

 

I also realized that my title is not completely correct, as it is a pipeline reg with 'enable'.

 

I tried the same for a 'pure' pipeline reg like this :

  

	process(clock)
	begin
	   if rising_edge(clock) then
                reg_data_buffer <= s00_axis_tdata;
	   end if;
	end process;

or the 2nd version :

 

	process(clock)
	begin
	   if rising_edge(clock) then
                reg_data_buffer <= s00_axis_tdata;
           else
                reg_data_buffer <= reg_data_buffer;
	   end if;
	end process;

now the post synthesis schematic result is in both cases  note -the CE tied to VCC, because there is no 'enable' signal anymore in the process, hence a true pipeline reg.

 

pipeline reg - no enable.png

 

so it looks like the same result to me.

 

however I can understand the versions with the 'else' case are better coding style, as it is unambiguous . 

 

Q: I was just wondering : I thought latches could only be inferred in case a combinatoral process is written without an else case, but not when its a process with a clock in it's sensitivity list? 

 

** kudo if the answer was helpful. Accept as solution if your question is answered **
Moderator
Moderator
10,698 Views
Registered: ‎01-16-2013

Re: simple VHDL pipeline register

Yes, If else part is missing it should be inferred as latch.

Thanks,
yash
Scholar ronnywebers
Scholar
10,692 Views
Registered: ‎10-10-2014

Re: simple VHDL pipeline register

hello @yashp, that sounds logical, but I see a different result in the synthesized schematic. Also I get no warning from the synthesis that a latch is inferred.

 

So I'm puzzled ...

** kudo if the answer was helpful. Accept as solution if your question is answered **
0 Kudos
Moderator
Moderator
10,682 Views
Registered: ‎06-24-2015

Re: simple VHDL pipeline register

@ronnywebers,

 

Also, since you have initialized reg_data_buffer(i.e. given a default value), they are not inferring latch.

You can refer this link on avoiding latches: http://electronics.stackexchange.com/questions/18075/how-to-avoid-latches-during-synthesis

Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).
0 Kudos
Xilinx Employee
Xilinx Employee
10,670 Views
Registered: ‎08-02-2011

Re: simple VHDL pipeline register

Q: I was just wondering : I thought latches could only be inferred in case a combinatoral process is
written without an else case, but not when its a process with a clock in it's sensitivity list?

This statement is correct. Neither of your code snippets above should infer a latch, nor do they.

 

Neglecting the else implies that there will be some conditions that are not covered and thus the output doesn't change. It holds it's previous state. The way that gets inferred by the synthesis tool depends on whether that's in a clocked or combinatorial process. In the former case, the code describes a register. In the latter, it is a latch.

 

In your code snippets, both are clocked processes so they'll infer the same logic.

www.xilinx.com
Instructor
Instructor
10,660 Views
Registered: ‎08-14-2007

Re: simple VHDL pipeline register

Just to be clear, a self-assignment like:

 

  reg_data_buffer <= reg_data_buffer;

 

has no effect unless it is overriding an earlier assignment.  In your code, it is not overriding another assignment because the only other assignment is in the "if" branch" and the self-assignment is in the "else" branch.  Thus the two code samples are equivalent.

 

Also note that completing an if/else or case statement using self-assignment will not prevent latch creation in the case of a combinatorial process.  i.e. if your process as written were not clocked, adding the else clause with a self-assignment would still make no difference.  The following two processes are also equivalent and both will infer transparent latches:

 

process(s00_axis_tvalid,s00_axis_tdata)
  begin
     if s00_axis_tvalid = '1' then
            reg_data_buffer <= s00_axis_tdata;
           end if;
  end process;

process(s00_axis_tvalid,s00_axis_tdata)
  begin
     if s00_axis_tvalid = '1' then
            reg_data_buffer <= s00_axis_tdata;
           else
            reg_data_buffer <= reg_data_buffer;
           end if;
  end process;

 

I generally prefer not to add the else clause when the assignment in it has no effect.  Whether or not you do so is a matter of style only.

-- Gabor
Historian
Historian
10,659 Views
Registered: ‎01-23-2009

Re: simple VHDL pipeline register

In most circumstances, the two codes will produce identical results. But there is a subtle difference between them.

 

The first one (directly) infers a flip-flop with a CE.

 

The second one infers a flip-flop with a MUX in front of it that recirculates the Q back to the D.

 

These are fundamentally the same thing, and the synthesis tool is almost certainly going to recognize that and use the form that it wants - and there are advantages to both

  - the first one (with the CE) use only a Flip-Flop whereas the second one uses a LUT and a Flip-Flop

  - the first one uses a control set where the s_axis_tvalid is used as a CE whereas the second one uses a control set with no CE

     - this means that the first one can only be placed in the same slice as other FFs with this CE; the second can be placed in the same slice as any other FF that uses no CE (which is more common)

 

Generally the tool will make the decision to convert from the first to the second if necessary (this is control set reduction). I am always less optimistic that it can recognize the MUX and convert it back to the CE (but, as shown by your example, it appears to be able to).

 

As an interesting side note, take a look at the Elaborated (not synthesized) design - I wonder if that will show the difference in the coding style (which gets optimized later).

 

Finally, the second form is more verbose. Given that there is no advantage to this form, I would avoid the verbosity.

 

Avrum

Highlighted
Historian
Historian
10,656 Views
Registered: ‎01-23-2009

Re: simple VHDL pipeline register

It's amazing how often this confusion comes up regarding latches and else-less if statements.

 

(First, the response from  @balkris and @yashp  that say this will infer a latch are incorrect. Similarly the response from @nupurs that the initialization prevents latch inference is also incorrect...)

 

The rules are really very simple. Start by "think hardware" - the RTL description provided by the code will map to some hardware. You need to think about the functionality of the code written and simply ask yourself "What hardware construct can do exactly what is described by this RTL code".

 

 

But here are some simple rules...

 

1) A latch can NEVER be inferred in a clocked process

2) An else-less if in a combinatorial process will produce a latch (in fact, any time a signal is assigned in some conditions by not in all conditions)

3) Even in a combinatorial process, the assignment of a signal to itself will not prevent the inferring of a latch

    - in fact, it is explicitly coding a latch!

 

always @(*)

begin

  if (en)

     q <= d;

  else

     q <= q;

end

 

This says that if the "en" is deasserted, the q has to hold its value. How can it hold its value if it is a purely combinatorial signal; it can't!

 

So:

  - this is not a combinatorial signal (since it needs to hold its value)

  - this has no sensitivity to the clock so it is not a flip-flop

  - therefore this is a latch!

 

always @(*)

begin

  if (en)

     q <= d;

end

 

This is exactly the same - if the en is asserted, then q takes the value of d. If en is not asserted q is not updated, and hence retains the same value. So this is a latch!

 

Anything that has the form

 

always @(posedge clk)

begin

   ...

   q <=

end

 

Is a Flip-Flop.

 

always @(posedge clk)

begin

  if (en)

     q<= d

end

 

This clearly states that if en is asserted, then q will take the value of d on the next rising edge of clock. This is a flip-flop (with enable). If en is not asserted, then q doesn't change its value. As opposed to a combinatorial signal, this is not a problem for a flip-flop - in fact, this is the exact intent of a flip-flop. Therefore this is a flip-flop.

 

Avrum

Scholar ronnywebers
Scholar
5,924 Views
Registered: ‎10-10-2014

Re: simple VHDL pipeline register

Thanks all for the great & detailed explanations @avrumw@gszakacs@bwiec@nupurs@yashp

 

It's true that - as @avrumw states - this subject is very confusing, that's because many blog sites and forum posts that I read are just plain wrong, and most books don't go as detailed on this 'potential latch inference' problem as is explained by you people in this forum thread. Me as an engineer, I don't take all these posts for granted, so I continue until I find the truth :-) So thanks again all for taking your time to do this, and thanks @avrumw for this detailed and precise answer.

 

@avrumw I'll check the elaboration results right away

 

 

note : this thread / question actually arose from an issue I had with the simulator, posted here, in which I was suspecting that my hdl code for the pipeline register (as in my very first version) was wrong. But in the end it appears to be a stimulus issue in the testbench. So my first version of the pipeline register was working fine, it were just my stimuli that were badly aligned to the clock.

** kudo if the answer was helpful. Accept as solution if your question is answered **
0 Kudos