UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor jjf_valar
Visitor
7,081 Views
Registered: ‎03-02-2013

some problems about PCAP and Partial Reconfiguration Controller

        Hi, I am using the partial reconfiguration function on the Zynq 706 board,  and recently I have found some problems about partial reconfiguration function compared with the ML605 board. For Zynq seriel FPGAs, we can use PCAP, Partial Reconfiguration Controller, AXI_HWICAP and the ICAP Processor, and those methods are described in Xilinx providered workshop. So there are some problems I want to discuss as following:

 

1. Compared with Virtex6 chips and ISE design tool, I think Zynq and Vivado has more advanced and complicated protection mechanism for reconfigurable modules, such as decoupler. User can shutdown the reconfigurable module before the reconfiguration process to avoid exceptions, so can you tell me some detailed protection mechanism for reconfigurable module?

 

2. I have run the PCAP lab in the worshop, this PCAP lab contians a reconfigurable module rp_math which can be configured as multiplier or adder. I found a very interesting problem. First I download the complete bitstream including adder, then I operate the adder function, the system is corrupted! Software failed to access the registers in the adder function!!! Second I download the same complete bitstream including adder, then I use PCAP to reconfigure the rp_math module with adder, then I operate the adder function, it worked fine. So why the first operation failed and the second operation worked? why the module won't work untill I reconfigure it???

 

3: I have run the Partial Reconfiguration Controller(PRC) lab in the workshop and it works well. But then I make some function improvement in this lab. I replace the function in the reconfigurable module with a image processing IP generated by the High Level Synthesis(HLS). Actually I use  HLS designed two function templatematch(MATCH) and search minimal value(SEARCH), then the two function will be designed as partial reconfigurable in one reconfigurable module. Because the IP is axi4stream interface, I use a DMA to driver it. The DMA is not in the reconfigurable module and it is static logic. When I test the result, I found another deally problems. The two complete bitstreams contains MATCH and SEARCH works fine, so I known that my design is right. The I test the partial reconfiguration process. When the reconfigurable module is configured as MATCH, I reconfigured it with SEARCH, then I operate it, it will generate the wrong result for the first time, but the following operation result is right!!! When the reconfigurable module is configured as SEARCH, I reconfigured it with MATCH, then I operate it, the DMA failed!!! The DMA receive channel is always busy and failed to receive the data!!! Do someone has similar problem about the design with DMA + PRC ?? I have studied this problem for several days and I still can not figure it out.

 

Thank you for any help!

0 Kudos