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Explorer
Explorer
6,239 Views
Registered: ‎04-07-2013

timing summary show very low frequency

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Hi,

 

I found that the Maximum frequency of my project is quite low. I generated TriMac and MIG core by Core Generator and merge the ucf files from their example designs as a ucf file of my design.  I have test my design on board, it works well.

 

I also check the example design of Trimac, the timing summary also show its maximum frequency is around 7MHz.

 

My ucf file is enclosed, could you please check it?

 

 

Timing summary:
---------------

Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0)

Constraints cover 391019 paths, 0 nets, and 149724 connections

Design statistics:
Minimum period: 194.040ns{1} (Maximum frequency: 5.154MHz)
Maximum path delay from/to any node: 7.599ns
Minimum input required time before clock: 1.298ns

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Teacher muzaffer
Teacher
9,825 Views
Registered: ‎03-31-2012

Re: timing summary show very low frequency

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this is probably not about your constraints but about your design. Post your worst case timing path so that someone can comment on how to make it faster.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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Explorer
Explorer
6,210 Views
Registered: ‎04-07-2013

回复: timing summary show very low frequency

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The project is compiled by ISE 14.6
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Teacher muzaffer
Teacher
9,826 Views
Registered: ‎03-31-2012

Re: timing summary show very low frequency

Jump to solution
this is probably not about your constraints but about your design. Post your worst case timing path so that someone can comment on how to make it faster.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
0 Kudos