04-09-2015 11:54 AM - edited 04-09-2015 06:18 PM
I found via chipscope a timming issue in my design.
The FSM should only jump to another state when the counter cnt512toN == 'd511 and the counter rd_ram_cnt == 'd4
but I can see from chipscope that it jumps when cnt512toN = 0 && rd_ram_cnt == 'd4.
It seems that the register of cnt512toN has a long delay. I've tried reducing the FSM states, duplicating the cnt512toN register, but the timing issue still exists.
I attach the chipscope capture and my code. Please check it and help me. Thank you very much.
04-09-2015 01:45 PM
Simple questions first. You are applying timing constraints correct?
And the design passes timing correct?
The code below doesn't include the chipscope logic, I'm assuming you used the inserter. What clock is the chipscope logic setup to sample with? (Your design has two clocks - if you hooked up chipscope to the wrong one you'd see weird transitions.)
Have you verified all cross clock domain paths? How?
04-09-2015 05:28 PM
what is #DLY doing in your code?
can you explain a bit about it?