GMACS = Giga MAC per second, so it also depends on the clock frequency DSP block is operating at. Each DSP48 block in Virtex7 has a pre-adder in it, so it can do two MAC's ((A+D)*B) per clock cycle. The Fmax of DSP48 block in Virtex7 is 638MHz (-3 speed grade), so here is how 6737GMACS is calculated:
Max GMACS = 5280 DSPs * 638MHz * 2 = 6737 GMACs
@dmitrip wrote:
Hello,
I notice that "DSP throughput (symmetric filter)" is given in units of GMACS for the Virtex-7 family (up to 6,737 GMACS) (here: http://www.xilinx.com/products/silicon-devices/fpga/virtex-7/index.htm). Multiplication and accumulation is great, but could someone help me understand what operations are being counted? I see that the Virtex-7's have a few thousand DSP slices, but I'm not sure what Xilinx has in mind to get that performance (apparently not 1 MAC per DSP slice per clock cycle).
I would like to do digital filtering in single or double precision, probably using a xilinx floating-point core, and would like to understand how many multiply accumulate operations I can get out of a given board.
Thanks
Cheers,
Jim
