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Registered: ‎08-23-2011

using synplify for synthesis from within ISE 14.5 for coregen core ...

Hi, I think this may still qualify as a xilinx question (and not a synplify pro question) because i am using synplify pro from within xilinx ISE 14.5 ONLY FOR SYNTHESIS. So here goes ...


i'm coding in verilog. i made a small fifo using xilinx coregen and included it in my verilog design. i ran synthesis using synplify pro and it went through without errors. however, when i look at the synplify log file, it shows a warning saying -


"creating black box for empty module <fifo instance name>" and i don't see synplify calling the xilinxcorelib for the fifo core (but it does search for other libs like unisim, simprim etc.)


furthermore, when i implement the design (i.e. run translate/map/P&R) using xilinx ISE 14.5, that also goes through without any errors but in the xilinx design summary i get warnings which indicate that "all the input signals to the fifo core have been removed".


my questions - 


1) is there any special method to use/instantiate xilinx coregen cores while synthesizing using synplify?

2) how do i point synplify to the xilinxcorelib (if needed)?

3)do i need to include the core's .ngc file inside synplify or does it happen automatically?

4) are the warnings ok?

5) anything that i may have missed out?


ive added the synplify log (main_compiler.doc) file for reference.


thanks for your inputs.




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Xilinx Employee
Xilinx Employee
Registered: ‎09-20-2012

Re: using synplify for synthesis from within ISE 14.5 for coregen core ...


Check this thread http://forums.xilinx.com/t5/Synthesis/Using-Coregen-cores-with-Synplify/td-p/88286

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