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girishs12
Visitor
Visitor
5,380 Views
Registered: ‎09-19-2009

variable SRAM on FPGA

i'm plannig to design a variable sram on fpga and interface it to micro controller.. i know it'll be a waste of resources if i design only a sram but, i'm starting with it.

I have found info from this link

http://www.geocities.com/SiliconValley/2072/ramworks.htm

I need info on how to go about the design. I will be using VHDL/verilog for the code.

Any suggestions??

Girish

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shantanu75
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5,360 Views
Registered: ‎04-06-2009


girishs12 wrote:

i'm plannig to design a variable sram on fpga and interface it to micro controller.. i know it'll be a waste of resources if i design only a sram but, i'm starting with it.

I have found info from this link

http://www.geocities.com/SiliconValley/2072/ramworks.htm

I need info on how to go about the design. I will be using VHDL/verilog for the code.

Any suggestions??

Girish


Hi Girish,

 

Try to use Device Premitive Block RAM as single port RAM and instantiate them in your code according to your requirement.

 

Shantanu Sarkar
http://www.linkedin.com/pub/shantanu-sarkar/0/33a/335
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girishs12
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Registered: ‎09-19-2009

Thanks Shanthanu

ICan Block RAM  be interfaced to Micro controller?

Whats the diff between SRAM on FPGA and Block RAM??

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bassman59
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Registered: ‎02-25-2008


girishs12 wrote:

Thanks Shanthanu

ICan Block RAM  be interfaced to Micro controller?


Yes, it's very simple, just bring out the appropriate BRAM connections to FPGA pins.

 

 


Whats the diff between SRAM on FPGA and Block RAM??


Ignore, for a moment, the fact that the entire FPGA configuration is stored in SRAM after start-up.

 

All memory internal to the FPGA is static. BRAM is one of two types of these memories; the other is Distributed (LUT) RAM. The User Guides for the various device families explain the differences in detail.

----------------------------Yes, I do this for a living.
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martinthompson
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Registered: ‎08-14-2007

One difference between "SRAM" and blockram is that SRAM (in the microcontroller world) often means asynchronous RAM, whereas the BRAMs are synchronous, so they always need a clock, and the data out appears one tick after the address is presented.

 

Also, micros are usually designed to attach to a bidirectional databus, wheras the BRAMs have separate DIN and DOUT pins, so you'll need some tristates in your FPGA to make sure that the DOUTs don't drive the external bus when the micro is trying to write to the BRAM

 

Martin Thompson
martin.j.thompson@trw.com
http://www.conekt.co.uk/capabilities/electronic-hardware
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