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anee_anil
Adventurer
Adventurer
3,720 Views
Registered: ‎01-16-2008

vhdl code help

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Hi all,

 

I have to send  1 D array  at each  rising edge of the clk. below is my code please help me to complete the code.

 

entity data_sense is
port(       clk : in std_logic;
             --addr : in integer range 0 to 3;
         data_out : out std_logic_vector(15 downto 0));
end data_sense;

architecture Behavioral of data_sense is
type vector_array is array(0 to 3) of std_logic_vector(15 downto 0);
signal memory : vector_array;
signal addr  : integer range 0 to 3;
--type vector_array1 is array(0 to 3) of std_logic_vector(15 downto 0);
--signal temp : vector_array1;
signal temp : std_logic_vector(15 downto 0);
begin
memory(0)(15 downto 0) <= "1111000011110000";
memory(1)(15 downto 0) <= "1111000011110000";
memory(2)(15 downto 0) <= "0111000011110000";
memory(3)(15 downto 0) <= "1111000011110000";
process(clk)
--variable temp : std_logic_vector(15 downto 0);
begin
for i in 0 to 3 loop
if(clk'event and clk = '1') then
temp <= memory(i)(15 downto 0);
end if;
end loop;


end process;
data_out <= temp;

end Behavioral;

I have to send 4 array one by one repeatedly at all the rising edge of the clk :)

 

Please help.

 

Thanks

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1 Solution

Accepted Solutions
sridar
Explorer
Explorer
4,402 Views
Registered: ‎09-20-2007

Hi,

You can use ROM based approach for this.

 Example code is below

 

entity romapproach is
   
    Port ( clk : in  STD_LOGIC;
          dout : out  STD_LOGIC_VECTOR (15 downto 0));

end romapproach

architecture Behavioral of romapproach is

 type data is array (0 to 3) of std_logic_vector (15 downto 0);
 Signal SData : data:=  (  "1111000011110000","1111000011110000","0111000011110000","1111000011110000");

 Signal dcount : integer range 0 to 3;
   
begin


Process (clk)

begin

If rising_edge (clk) then

   dout <= Sdata(dcount);

 if (dcount = 3) then
 
  dcount <= 0;

  else dcount <= dcount+1;
 
  end if;
 
end if;

end process;

end Behavioral;
 

 

FPGA freak

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2 Replies
sridar
Explorer
Explorer
4,403 Views
Registered: ‎09-20-2007

Hi,

You can use ROM based approach for this.

 Example code is below

 

entity romapproach is
   
    Port ( clk : in  STD_LOGIC;
          dout : out  STD_LOGIC_VECTOR (15 downto 0));

end romapproach

architecture Behavioral of romapproach is

 type data is array (0 to 3) of std_logic_vector (15 downto 0);
 Signal SData : data:=  (  "1111000011110000","1111000011110000","0111000011110000","1111000011110000");

 Signal dcount : integer range 0 to 3;
   
begin


Process (clk)

begin

If rising_edge (clk) then

   dout <= Sdata(dcount);

 if (dcount = 3) then
 
  dcount <= 0;

  else dcount <= dcount+1;
 
  end if;
 
end if;

end process;

end Behavioral;
 

 

FPGA freak

View solution in original post

anee_anil
Adventurer
Adventurer
3,658 Views
Registered: ‎01-16-2008

Thanks sridar,

 

The code is working as i expected :)

 

with regards

ANIL

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