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prakece25

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02-23-2010 10:56 PM

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02-11-2010

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prakece25

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03-08-2010 12:47 AM

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actually i am doing program for integer division .numerator has lot more variables to be added . The denominator has only integer of 20.But xilinx is not accepting this division since it can accept only denominator should be of power of 2.

xkp00<=conv_std_logic_vector(conv_integer(fns(0))*conv_integer(xkp00)/20-8*conv_integer(xkp11)/20+48,10) ;

this is one of my coding line here only the denominator part 20 is not accepted . instead if i put 16+4 there is no error but the output is not coming properly.ie it shows all the outputs are 0.

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bassman59

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02-24-2010 09:14 AM

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prakece25 wrote:if anyone have coding for division in vhdl please do help me

entity divider is

port (

divisor : in integer;

dividend : in integer;

result : out integer);

end entity divider;

architecture dothemath of divider is

begin

result <= dividend / divisor;

end architecture dothemath;

----------------------------Yes, I do this for a living.

drjohnsmith

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02-25-2010 06:48 AM

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Hi

can I ask what type of division . in time ( counter ) or in maths.

Integer, fixed point, floating point, divide by a constant or a variable ?

If you have a multiplier / divider it could be easy, if you have not, then its a big tree of code, or a rom.

The question is really what do you want to divide and by what ?

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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prakece25

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03-08-2010 12:47 AM

14,365 Views

Registered:
02-11-2010

actually i am doing program for integer division .numerator has lot more variables to be added . The denominator has only integer of 20.But xilinx is not accepting this division since it can accept only denominator should be of power of 2.

xkp00<=conv_std_logic_vector(conv_integer(fns(0))*conv_integer(xkp00)/20-8*conv_integer(xkp11)/20+48,10) ;

this is one of my coding line here only the denominator part 20 is not accepted . instead if i put 16+4 there is no error but the output is not coming properly.ie it shows all the outputs are 0.

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drjohnsmith

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03-08-2010 03:51 AM

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HI

can I ask have you looked at what hardware this is generating ?

This looks like C code.

You have defined three inputs to a multiplier,

fns(0) , ( xkp00/ 20 ) - 8, and (xkp11/20)+48

and returned the answer to 10 bits.

For the inputs, you have deifned two divider, I assume 32 bit integers each xkp00 / 20 and xkp11/20.

You have also defined a subtractor and an adder, probably on 64 bits.

Not the most efficient implimentaiont in hardware I guess.

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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bassman59

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03-08-2010 09:41 AM

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prakece25 wrote:actually i am doing program for integer division .numerator has lot more variables to be added . The denominator has only integer of 20.But xilinx is not accepting this division since it can accept only denominator should be of power of 2.

xkp00<=conv_std_logic_vector(conv_integer(fns(0))*conv_integer(xkp00)/20-8*conv_integer(xkp11)/20+48,10) ;

this is one of my coding line here only the denominator part 20 is not accepted . instead if i put 16+4 there is no error but the output is not coming properly.ie it shows all the outputs are 0.

You're not "doing a program." You are describing hardware. There is a significant difference. You must understand this.

----------------------------Yes, I do this for a living.

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prakece25

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03-10-2010 04:17 AM

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thank u drjohnsmith but for simulation can i clear the error

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prakece25

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03-10-2010 04:20 AM

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drjohnsmith

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03-10-2010 04:53 AM - edited 03-10-2010 05:10 AM

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07-09-2009

HI

significant differance. do you want to simulate only, or do you want to generate real silicon ( synthesise ).

Seems your using std logic arith, which in most places I go to is a big no no.

anyway.

You also have to look at order of ooperation even for synthesis.

xkp00<=conv_std_logic_vector( [ conv_integer(fns(0)) * conv_integer(xkp00)/20 ] - [ 8 *conv_integer(xkp11)/20 ] + 48 ,10 )

I've added some brackets ( in [ ] ) just to show you what the synth is actualy doing ( it won't synth like that ).

Spliting this out

A, B, C, D and E are 32 bit integers.

A <= conv_integer(fns(0));

B <= conv_integer(xkp00);

C <= B / 20;

D <= conv_integerxkp11);

E <= 8 * D / 20;

this gives a 32 bit integer result, which you thentake 10 bits of, I don't know whic 10 bits the funciton takes, I don't use it.

xkp00 <= conv_std_logic_vector ( ( A * C ) - E + 48, 10 ); -- i.e. take 10 bits

Is that the expresion you were expecting ?

A feature of MATLAB, that catches every one,

MATLAB work in floating point or integers of width X. Whilst VHDL works in integers of width Y, and preferable std_logic_vectors of width Z.

It's up to you to make certain you get the correct bits in MATLAB.

typical for something like this, the nearer your MATLAB code is like the VHDL with fixed size numbers, the better is will synthesis to good VHDL.

Message Edited by drjohnsmith on 10-03-2010 01:10 PM

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prakece25

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03-11-2010 04:19 AM

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02-11-2010

thank u drjohnsmith u hav given

A, B, C, D and E are 32 bit integers.

A <= conv_integer(fns(0));

B <= conv_integer(xkp00);

C <= B / 20;

D <= conv_integerxkp11);

E <= 8 * D / 20;

xkp00 <= conv_std_logic_vector ( ( A * C ) - E + 48, 10 ); -- i.e. take 10 bits

if i do take the codings like this , will it work or not. i am taking here only 10 bits for my purpose

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drjohnsmith

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03-11-2010 08:34 AM

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07-09-2009

Hi

that is your code,

just split out so it's easier to discuss.

As you can see, it's a lot of logic, so although it would synthesis, I would not want to do so.

For simulation, where you don't make silicon I can't see why it would not work.

It might also let you look at the 32 bit integers to see if your getting the intermediate values you expect.

e.g. what does B / 20 give you. is it a 32 bit answer or 64 bits ? if 64 bits, what happens to the other 32 bits if you assign it back to a 32 bit integer ?

In matlab or C etc, where everything is floating points, you ignore this,

In DSP or FPGA world, you need to know the size of your numbers, and what happens to them

for instance, your conv_std_logic_vector functioni from synopsis.

what does this do to a 32 bit integer ?

Does it take the top 10 , bottom 10 , middle ten bits, round off / up or what ? You have to know.

and it all depends where your data is sat in the integer. If it's all at the top end, then if the convert is taking the bottom 10 bits, then your going to get 0 out of the equaiton.

put it in a simulator, step throught a few numbers and see what each of the integers are,

You might be surprised.

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

prakece25

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03-12-2010 12:09 AM

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02-11-2010

thank u drjohnsmith

i am taking here only the LSB 10 bits.But this coding is ok for model sim it also shows the output .but for implementation i need to work with xilinx. that's why i post here. but i need only 10 bit output.if i send u the coding would you clear the error?

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drjohnsmith

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03-12-2010 02:32 AM

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07-09-2009

Hi

just to clarify, I don't work for xilinx.

I'm an independent consultant,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

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prakece25

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03-14-2010 10:57 PM

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Thank you drjohnsmith

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praveensimbhu_86@yahoo.co.in

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05-03-2010 01:26 AM

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05-03-2010

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drjohnsmith

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05-03-2010 09:49 AM

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07-09-2009

Hi

will it work? Yes, it's psedo code, so naturaly.

Will it give you the answer your expecting ? unlikely.

You have not answered the fundamental questions we asked you above, and until you do, it is not going to give the answer you expect !

Ok, on paper, put some numbers in for fns(0) and xkp00 and work out what you expect from xkp00 !

Can we see you results ?

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goelrahulgoel

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08-06-2013 01:51 AM

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02-17-2013

hello i am writing a program for configuration declaration in this program i am making two architecture by one entity . in this program when i am compaling then last architectutre is compaling which is count_255. but i want execute architecture count_64k . how it can possible pls help me

---------------------------------------------------------------------

LIBRARY IEEE;

USE IEEE.std_logic_1164.ALL;

ENTITY counter1 IS

PORT(load, clear, clk : IN std_logic;

data_in : IN INTEGER;

data_out : OUT INTEGER);

END counter1;

ARCHITECTURE count_64k OF counter1 IS

BEGIN

PROCESS(clk)

VARIABLE count : INTEGER := 0;

BEGIN

IF clear = '1' THEN

count := 0;

ELSIF load = '1' THEN

count := data_in;

ELSE

IF (clk'EVENT) AND (clk = '1') THEN

IF (count = 65535) THEN

count := 0;

ELSE

count := count + 1;

END IF;

END IF;

END IF;

data_out <= count;

END PROCESS;

END count_64k;

ARCHITECTURE count_255 OF counter1 IS

BEGIN

PROCESS(clk)

VARIABLE count : INTEGER := 0;

BEGIN

IF (clear = '1') THEN

count := 0;

ELSIF load = '1' THEN

count := data_in;

ELSE

IF (clk'EVENT) AND (clk = '1')

THEN

IF (count = 255) THEN

count := 0;

ELSE

count := count + 1;

END IF;

END IF;

END IF;

data_out <= count;

END PROCESS;

END count_255;

CONFIGURATION small_count OF counter1 IS

FOR count_255

END FOR;

END small_count;

CONFIGURATION big_count OF counter1 IS

FOR count_64k

END FOR;

END big_count;

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ccon67

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08-15-2013 02:03 PM

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01-21-2011

@bassman59 wrote:

prakece25 wrote:

You're not "doing a program." You are describing hardware. There is a significant difference. You must understand this.

They hired me to make those FPGA alive

they call me 'software' or 'coding' engineer or similar such name

I refuse the name, but I take $$$

:-)

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