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Observer
Observer
7,462 Views
Registered: ‎03-15-2011

where can I post my code?

Hello,

 

Im learning verilog and im using xilinx.. this forum confuses me and i dont know if there is any general help section cause i cant find it.

 

I wrote a simple program.. its supposed to be a timer, but its not working. is there any place here where i can post the code and get comments from you guys?

 

 

Thank you

 

<EDIT> k so after browsing this forum i found that there are topics of similar nature here and my code can be posted here :)

 

What im trying to do is to create a simple system, a part of it is an irq timer module... its supposed to generate a pulse determined by a parameter and each pulse should last for 4 clock cycles.

here is what i worte (its my first verilog module)

 

Note: i have no idea how to implement parameter here, i know that its implemented using the leyword parameter in the module header but i dont know how it can be used here for our purpose.

Note: clock is supposed to be 32768 Hz, am i supposed to mention thsi someplace in my code?

 

 

module timer(
input clock,
input reset,
output reg[15:0] irq
);

always@(posedge clock or posedge reset)
begin
if(reset || (irq==16'h8000))
irq<=0;
else
irq<=irq+1;

end

endmodule
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Observer
Observer
7,455 Views
Registered: ‎03-15-2011

Re: where can I post my code?

i chose 16 bits as the clock 32768 when converted to binary is 16 bits
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Instructor
Instructor
7,446 Views
Registered: ‎07-21-2009

Re: where can I post my code?

Im learning verilog and im using xilinx.

Two good choices!  You're off to a good start.

I wrote a simple program.. its supposed to be a timer, but its not working.

What does "not working" mean?  Is this a simulation, or are you running on actual hardware?

its supposed to generate a pulse determined by a parameter and each pulse should last for 4 clock cycles.

I've modified your code to generate a 4-cycle pulse.  Pasted below.

here is what i wrote (its my first verilog module)Note: i have no idea how to implement parameter here, i know that its implemented using the keyword parameter in the module header but i dont know how it can be used here for our purpose.

Here is a good website for starting with Verilog and FPGA design.  Links to HDL tutorials here.

Here is an excellent Verilog "cheat sheet".

Finally, check the language templates which Xilinx provides along with ISE.  Go to EDIT > Language Templates.  You will find parameters described in the Synthesis Constructs section, under Signal Constant and Variable Declaration.

Note: clock is supposed to be 32768 Hz, am i supposed to mention thsi someplace in my code?

Are you using a 32768Hz clock or are you generating a 32768Hz clock from a higher frequency clock?  Nothing you put in your code will change the frequency of a clock input.  If you are synthesising a new clock frequency from a clock input with a different frequency, this you can do by adding a PLL or DCM or equivalent to your design.

 

Notable changes from your original code are marked in red.

 

In your original code, you mixed an async reset function (signal reset) with a synchronous logic reset in a single line.  This may synthesise correctly (not sure), but this is bad form.  You should keep async reset separate from a sync clear or init.  They are two different hardware paths or functions.

module timer(
input clock,
input reset,
output reg[15:0] irq = 0,
output wire pulse
);

always @(posedge clock or posedge reset)
begin
if (reset) irq <= 0; // async reset all by itself
else if (irq==16'h8003)) irq <= 0; // terminal count, wrap to 0
else irq <= irq+1; // counting normally
end

assign pulse = irq[15]; // asserted for 4 cycles

endmodule

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Observer
Observer
7,408 Views
Registered: ‎03-15-2011

Re: where can I post my code?

Thanks a lot for your detailed reply. This one reply helped me lots and the language templates resource was excellent. I did not know about it before this :/

 

sorry i did not explain not working properly. I am simulating this program using Isim.. and the simulation gave me a stream of x's.

 

But thanks to your help its working now to some extent..

 

I was also able to generate the clock by myself as well .. did some digging around and found out that we have to write the code for clock in test bench.. and here i expected verilog to do this for us. ill attach that code as well.

 

i dont know why but adding the wire decaration in header like you did gave me an error, also writing output with it also gave me an error, "output pulse is unknown". here is the code that is simulating properly, thanks to you :)

 

 

module timer_final(
    input clock,
    input reset,
    output reg[15:0] irq=0
    );

wire pulse;

always@(posedge clock or posedge reset)
begin
	if(reset) irq<=0;
	else if(irq==16'h8003) irq<=0;
	else irq<=irq+1;
end

assign  pulse = irq[15];

endmodule

 

I would appreciate if you could clear up some of my confusions regarding the code.. i understand you used this line to generate a pulse that maintains for 4 clock cycles: 

 

assign  pulse = irq[15];

but i dont know how this is supposed to do that, as the line does not mention anything about 4 clock cycles, nor is it in a repeat loop.. its just assigning the output of a reg to a wire.. can you please tell em why this line was added?

or why even need a wire? is it necessary for every module with an output? why didnt we use wires for the inputs then?

 

my apologies for my basic questions. :/

 

also i simulated this and it went fine without errors and this is what i got:

 

meh1.png

 

as can be seen the output is not maintained for 4 clock cycles... or is it?? lol maybe i cant tell,, but irq output is maintained for 1 clock cycle..

 

can the repeat keyword be used to get the 4 clock cycles?

 

Also this generates interrupts at regular intervals, how can we change this to give output determined by a parameter.. the only way I can think of is to add or divide parameter with always@(posedge clock) but that doesnt make sense and obviously that wont work.

 

Sorry about ths long post.. Thank you for your help.

 

Also ill add my test bench code here as well:

 

 

module test_timer_final;

	// Inputs
	reg clock;
	reg reset;

	// Outputs
	wire [15:0] irq;

	// Instantiate the Unit Under Test (UUT)
	timer_final uut (
		.clock(clock), 
		.reset(reset), 
		.irq(irq)
	);

	//Code for 32768Hz Clock
	initial begin
	clock=0;
	forever
		#15259 clock=~clock;
	end
	
	initial begin
		// Initialize Inputs
		clock = 0;
		reset = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
	
	end
      
endmodule

 

 

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Instructor
Instructor
7,402 Views
Registered: ‎07-21-2009

some lessons in coding

It sounds like you are learning a lot.  Good for you!

I would appreciate if you could clear up some of my confusions regarding the code.. i understand you used this line to generate a pulse that maintains for 4 clock cycles: <line quoted>

You should be looking at the irq counter.  It cycles from 16'h0000 to 16'h8003 and then starts back at 16'h0000.  The most significant bit of this counter is irq[15].  From 16'h0000 to 16'h7FFF, irq[15] is '0'.  From 16'h8000 to 16'h8003, irq[15] is '1'.  So irq[15] is "high" for 4 counts, or 4 clock cycles, out of the complete cycle of the irq counter.

 

Does this make sense?  The wire "pulse" is only a copy of the counter bit irq[15].

 

Functionally, you do not need a separate module output port for "pulse".  Here's why I would add the port in my own designs (and this is something you learn as you write more code):

 

  • irq is simply a counter with no specific values implied or inferred.  You may change your timer module to count down instead of up, use a different counter width, change the counter encoding from binary to grey scale, etc. etc.  These changes might require coding changes where the timer module is being used.  In a small design, this isn't a big deal.  In a large design, this can be very inefficient and prone to mistakes and inconsistencies.
  • on the other hand, pulse has a specific function:  a 4-cycle pulse every "cycle" of xxxxx clock counts.  You can change the internals of the timer module (and the irq counter) while maintaining the meaning of the "pulse" output.  By doing this, you (more or less) provide a defined interface for the module wherever the module is used, and internal coding changes to the timer module no longer require code changes where the timer module is used.

Does this make sense?

why didnt we use wires for the inputs then?

Basic rule:  wires and regs are defined where they are created, not where they are used.

 

You are learning rapidly.  Don't stop.  If you haven't already done so, you should invest in a good Verilog textbook for reference.  In most cases, the ability to immediately look things up yourself is much more handy than posting on a forum and waiting for a response.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Highlighted
Observer
Observer
7,389 Views
Registered: ‎03-15-2011

Re: some lessons in coding

Thank you for your detailed reply and yes thanks to you I am learning a lot as I am able to clarify my confusions and questions.. as before coming here I would just stare at the faulty code and hiope for it to magically work without any clock LOL..

ok so I got your concept of irq[15] and I think now I understand why you changed my irq==16'h8000 to 16'h8003.. as i got the idea for 'h8000 coz the clock 32768 converted to hex is 'h8000.

but its still a strange method for me.. and i would not have figured it out.. I was hoping for it to happen with some sort of loop, as the repeat or for loop..
is it possible any other way?

also the simulation i attached.. why is it not showing irq output for 4 cycles, i might be wrong but i think its only giving an intrerrupty for 1 clock cycle.

also I was thinking about the parameter thing as now this is generating a pulse at regular intervals, to make it generate at 10 nanosecond will this work.? (im not at my pc so i cant code it, so was just thinking:

 

 

module #(parameter delay = 10) timer_final(
    input clock,
    input reset,
    output reg[15:0] irq=0
    );

wire pulse;

always@(posedge clock or posedge reset)
begin
	if(reset) irq<=0;
	else if(irq==16'h8003) irq<=0;
	else irq<=irq+1;
end

assign  #delay pulse = irq[15];

endmodule

 so this way maintaining the output for some variable delay.. i'm pretty sure im completely off on this. =/

 

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Instructor
Instructor
7,387 Views
Registered: ‎07-21-2009

Re: some lessons in coding

I don't have time to help you debug your simulation, perhaps someone else can pitch in on this.

 

For your immediate purposes -- functional simulation -- do not bother with inserting signal delay.  Your simulation timing is (should be) measured in clock cycles, not nano-seconds.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Highlighted
Observer
Observer
7,132 Views
Registered: ‎03-15-2011

Re: some lessons in coding

Hi.. long time cause i was busy with my exams. but im free again.

 

I understand.. But I left this recently and started working on new modules.

 

im making a module that just reads input and sends to output..

 

this can be done so easily in C, dont know why its so difficult in verilog..

 

however im gonna amke a new post for that. :)

 

thx for your help so far

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Historian
Historian
7,127 Views
Registered: ‎02-25-2008

Re: some lessons in coding

 


@ipunished wrote:

this can be done so easily in C, dont know why its so difficult in verilog..


 

 

 

Because C is a language designed for executing code on a sequential processor, whereas Verilog is used to describe the hardware implementation of a logic design? IOW, they are not at all similar.

 

FPGA design is hardware design. It is nothing at all like C programming.

----------------------------Yes, I do this for a living.
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Scholar
Scholar
7,108 Views
Registered: ‎09-16-2009

Re: where can I post my code?

 

Tell us more about what you mean when you say "it's not working".

 

It's not simulating correctly?  (You ARE running simulations correct?).

 

It's not synthesizing correctly?

 

It's not working on a lab bench on real FPGA hardware?

 

Syntactically, you're code looks ok.  It doesn't do quite what you want, but

it's a good start.  I see some things that the synthesizer might not like.

 

Tell us more about what you tried - what worked, what didn't?

 

--Mark

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Scholar
Scholar
1,639 Views
Registered: ‎09-16-2009

Re: where can I post my code?

Sorry folks - I only just saw the OP and just replied. Didn't see any
of the followups until after I hit send. Weird...
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