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Visitor groupeeseo
Visitor
4,579 Views
Registered: ‎02-17-2014

xadc and system generator

hello everyone,

I have a kintex 7 KC705 with an XADC analog to digital converter integreted in the card.

I would like to use this ADC inside a system generator design but i do not how.

I saw tha vivado offers a wizard for XADC, i could try to configure the XADC with this wizard, than recuperate the generated  HDL codes inside system generator using a black box. even in this case i do not know how to do it, in detail... how  can I configure the analog input/ digital output; how can I generate the HDL codes from the vivado design?

Any suggestion or help will be reaaly appreciated

 

Best

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Xilinx Employee
Xilinx Employee
4,526 Views
Registered: ‎07-31-2012

Re: xadc and system generator

Hi,

 

Few Resource and guides for XADC.

 

Check Pg 369 of the 7 series library guide for the information and instantiation template for XADC wizard and also example instantiation template  in Pg 7 Series Library guide

 

1) http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf

2) Logicore XADC WIzard Guide

 

Thanks,
Anirudh

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Visitor groupeeseo
Visitor
4,517 Views
Registered: ‎02-17-2014

Re: xadc and system generator

thanks Anirudh for your kind answer. I had already had look to the documentation you suggested, I made some steps forward but still I cannot use the XADC inside system generator. My procedure is the following: I run vivado or logicore to design my XADC via the wizard, I recuperate the VHD codes and I assign them to a black box in system generator. This procedure creates an xilinx block with inputs and outputs. The problem is that I do not know what I have to link to the inputs of the created block, and how I can recuperate the digital data. In example there are input ports called DCLK or DO, I know that the come from the DRP but nowhere is written the FPGA pins they correspond to. Especially this DCLK looks to be very important for the XADC but as I said, I do not know the FPGA pin It corresponds to. Also the role or VP VN and GPIO ports is not clear to me, more in detail VP and VN are 1 bit ports? So can I use them as clock sources? And the two GPIOs are input or output, analog or digital? Thanks again for the help
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Xilinx Employee
Xilinx Employee
4,501 Views
Registered: ‎01-03-2008

Re: xadc and system generator

DCLK and DO are internal interface prts and do not connect to external pins of the FPGA. The VP and VN are external pins and are the analog differential input pins.
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