0 resource utilization after export IP for SC_METHOD based module
I got a strange problem.
I am trying to implement a systemC module in Vivado HLS which read data from BRAM, finish some simple math operations, and write results to another BRAM. I used ap_mem_port to define top mem interface according to UG902.
First I implement the module with SC_METHOD, and sim, syn (resource utilization is reported), and co-sim are all OK. But I found there is 0 resource utilization after I exported the design as IP catalog with "Vivado synthesis, place and route" option checked, and I further tried the behavior simulation with generated RTLs and xxx.autotb.v files, the module is not running, no signal change.
Then I switched to use SC_CTHREAD, and everything looks normal including behavior simulation with generated RTL in VIVADO, I got expected waveform.
Then I did other test, and found out if I don't use mem interface with SC_METHOD, everything is ok. Even "sc_uint<32> a[xx]" can not be used, otherwise the resource utilization will be quite less after exporting IP comparing to normal "C synthesis".
I also found the example projects, sc_fifo_port and sc_ram_port, both are using SC_CTHREAD instead of SC_METHOD, why?
Anybody know the reason?
I am using vivado system edition 2017.1, 30 days evaluation license.