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Observer
Observer
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Registered: ‎06-10-2019

128-bit bus with AXI4M_bus_port?

Given that AXI4M_bus_port does not seem to work with SystemC-like datatypes with Vivado HLS 2018.3, how should I implement a 128-bit bus port using the AXI4M_bus_port object?

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Observer
Observer
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Registered: ‎06-10-2019

We are still wondering on this issue. We are definitely interested in the answer, since some of the buses of the Xilinx Ultrascale MPSoC boards support up to a 128-bit width (such as some HP buses, as indicated by the MPSoC Datasheet Overview document, under the "Dynamic Memory Controller" section).

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Observer
Observer
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Registered: ‎01-12-2012

Any progress on this? I stumbled on this also!

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