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Adventurer
Adventurer
1,042 Views
Registered: ‎03-13-2015

2017.3 giving different results than 2017.2, despite no changes

The 2017.3 UG902 states "10/04/2017: Released with Vivado® Design Suite 2017.3 without changes from 2017.1.". I find this hard to believe. For this comparison, I am using the exact same sourcefiles, project and solution (including part) settings.

 

Using 2017.3, I get a lot slower result when synthesizing my function. The timing result is really bad on 2017.3 (13.47ns, vs 5.86 on 2017.2), and I get a load of warnings that 2017.2 didn't give. Like multiple warnings of this kind:

 

WARNING: [SYN 201-303] Root Node <x> mapped to expression {mul a b}, but failed in bitwidth check.

 

(What does this warning mean anyway?)

 

The failing path is also different, meaning 2017.3 probably chose a different way.

Now, I am thinking if any timing file changes could cause this bad result, but even if I relax the timing requirement from 6ns to 10ns, it is not able to find a solution. If a timing change cause this, it must have been really bad on 2017.2.

 

Also, I am asking myself if the 2017.2 version is safe to use?

I don't want to post my function here, but rather ask if there is something obvious I should check or add to my code.

 

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4 Replies
Moderator
Moderator
992 Views
Registered: ‎11-09-2015

Re: 2017.3 giving different results than 2017.2, despite no changes

Hi @cyviz,

 

The user guide (UG902) has not changed. This does not mean that the tool has not changed.

 

The UG973 gives a little more information about the changes but not all are documented.

 

Between versions, fixed are provided and there are enhancements to try to give better results...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
985 Views
Registered: ‎03-13-2015

Re: 2017.3 giving different results than 2017.2, despite no changes

Thanks florentw

 

I did open UG973 and searched for HLS, but apparently I have to search for "high level synthesis" to get there.

It says:

• Enhancements to the math.h library.

° Added functions for complete coverage.

° New native optimized support for half-precision floating point.

• Dataflow pragma supports loops with variable bounds.

• User assistance functionality enabled in co-simulation for ease of use.

 

I guess I got unlucky. I will stick to 2017.2 for now.

 

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Adventurer
Adventurer
979 Views
Registered: ‎03-13-2015

Re: 2017.3 giving different results than 2017.2, despite no changes

Maybe I should keep this thread going. Here is a very pecuilar feedback from the synth process:

 

WARNING: [SCHED 204-70] Unable to enforce a clock period constraint between 'select' operation ('sel_tmp44', <myfunction>.cpp:289) and 'br' operation.
In llvm assembly, the node are:
		
		.

 

 

Note, the empty line and the dot is exact copy from my output. (The function path and name has been hidden)

This does look like a bug in 2017.3? This 'sel_tmp44' is at the start of the very bad path reported.

 

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Moderator
Moderator
968 Views
Registered: ‎11-09-2015

Re: 2017.3 giving different results than 2017.2, despite no changes

Hi @cyviz,

 

There is not enough information to say if it is a tool issue or not...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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