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Visitor fkautz
Visitor
1,444 Views
Registered: ‎09-13-2017

AXI Master bundle / parallelization

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Hey, 

 

I guess following question will be easy for you guys to answer.

 

If I implement two AXI master ports in my HLS core which both are supposed to read data from the memory and I do not bundle them, I get 2 times all 45 RTL ports so 2 independent interfaces which can be connected to an interconnect separately.

So in my opinion it should be possible  that theoretically both copy processes could run in parallel.

 

If I now bundle those two AXI master, which is very common, to one interface I will logically only get 45 ports or one interface which can be connected to an interconnect. So that in my opinion copy processes are forced to be serialized.

 

Why is it common to bundle those interfaces? Just because most memories used are single ported anyway? Or do I have some serious problems in understanding what is happening?

 

Thanks!

BR

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Scholar u4223374
Scholar
1,820 Views
Registered: ‎04-26-2015

Re: AXI Master bundle / parallelization

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@fkautz That's correct. Obviously there are some scenarios where keeping it parallel makes sense (eg. the ZC706 and ZCU102 have two totally separate RAM banks, or one AXI Master can access something other than RAM) but most of the time combining them makes sense.

 

I've also had cases where I needed a "high-performance" AXI Master (doing 64-bit or 128-bit read/write burst transactions) and a separate "low-performance" AXI Master doing non-burst 32-bit transactions. HLS won't bundle AXI Masters with different bit widths.

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Scholar jprice
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1,400 Views
Registered: ‎01-28-2014

Re: AXI Master bundle / parallelization

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There are probably several reasons. The first that comes to mind is that it's expensive. Having extra interfaces in the HLS code and your interconnect consumes resources you may not want. The second reason is that if both ports are accessing the same memory, there's not a lot of point to serialization (there are exceptions like QDR where you can read/write at the same time). 

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Visitor fkautz
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1,384 Views
Registered: ‎09-13-2017

Re: AXI Master bundle / parallelization

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So if I am interpreting everything right ( and I guess you meant parallelization instead of serialization) it is like I said? The serialization forced by the single interface is no problem becaus all the memory access is serialized by  single port memory anyway?

 

Thanks

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Scholar u4223374
Scholar
1,821 Views
Registered: ‎04-26-2015

Re: AXI Master bundle / parallelization

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@fkautz That's correct. Obviously there are some scenarios where keeping it parallel makes sense (eg. the ZC706 and ZCU102 have two totally separate RAM banks, or one AXI Master can access something other than RAM) but most of the time combining them makes sense.

 

I've also had cases where I needed a "high-performance" AXI Master (doing 64-bit or 128-bit read/write burst transactions) and a separate "low-performance" AXI Master doing non-burst 32-bit transactions. HLS won't bundle AXI Masters with different bit widths.

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Visitor fkautz
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1,341 Views
Registered: ‎09-13-2017

Re: AXI Master bundle / parallelization

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@u4223374 thank you for the clarification! 

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