AXI-Stream FIFO Interrupt error

[jtkim]

Hi. 

I want to use only the axi-stream fifo receive complete interrupt. 

so i used rx interrupt example code from bsp.

When i used polling mode, it can operate normally.

However, when i used interrupt mode, it doesn't occur interrupt. It doesn't respone.

when i see the received tdata and valid from ILA, it is fine. 

So, in order to debug FIFO interrupt, when i click the FIFO registers in VITIS window, it occur the error interrupt(RPOREE & RPUREE). RDFD and RLR change continuously, i expect data value is correct. 

1) Can i use the receive interrupt by using only data and valid signal?

2) Why it doesn't provide interrupt, and i provide error interrupt pending signal when i click the register window?

Anyone helps me please.

Fifo interrupt code and configuration code is blow.

void Interrupt_Configuration(void)
{
/* ---------- Interrupt -------------------*/
XIntc_Initialize(p_intc, XPAR_MICROBLAZE_0_AXI_INTC_DEVICE_ID);

//Timer
XIntc_Connect(p_intc, XPAR_INTC_0_TMRCTR_0_VEC_ID, XTmrCtr_InterruptHandler, p_axi_timer_0_Timer);
XIntc_Enable(p_intc, XPAR_INTC_0_TMRCTR_0_VEC_ID);

//UART
//XIntc_Connect(p_intc, XPAR_INTC_0_UARTLITE_0_VEC_ID, XUartLite_InterruptHandler, p_uart_gps);
//XIntc_Enable(p_intc, XPAR_INTC_0_UARTLITE_0_VEC_ID);

//FIFO_VHF_DATA
XIntc_Connect(p_intc, XPAR_INTC_0_LLFIFO_1_VEC_ID, FifoHandler, p_axi_fifo_ping_data);
XIntc_Start(p_intc, XIN_REAL_MODE);
XIntc_Enable(p_intc, XPAR_INTC_0_LLFIFO_1_VEC_ID);

XLlFifo_IntEnable(p_axi_fifo_ping_data, XLLF_INT_RC_MASK|XLLF_INT_RXERROR_MASK);

//SPI
//XIntc_Connect(p_intc, , XPAR_INTC_0_SPI_0_VEC_ID, XSpi_InterruptHandler, p_axi_quad_spi_0_Spi);
//XIntc_Enable(p_intc, XPAR_INTC_0_SPI_0_VEC_ID);

//Interrupt Start
Xil_ExceptionInit();
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, XIntc_InterruptHandler, p_intc);
Xil_ExceptionEnable();

XIntc_Start(p_intc, XIN_REAL_MODE);

}

void FifoHandler(XLlFifo *InstancePtr)
{
static u32 Pending;

Pending = XLlFifo_IntPending(InstancePtr);
while (Pending)
{
if (Pending & XLLF_INT_RC_MASK)
{
FifoRecvHandler(InstancePtr);
XLlFifo_IntClear(InstancePtr, XLLF_INT_RC_MASK);
}
else if (Pending & XLLF_INT_TC_MASK)
{
FifoSendHandler(InstancePtr);
}
else if (Pending & XLLF_INT_ERROR_MASK)
{
FifoErrorHandler(InstancePtr, Pending);
XLlFifo_IntClear(InstancePtr, XLLF_INT_ERROR_MASK);
}
else
{
XLlFifo_IntClear(InstancePtr, Pending);
}
Pending = XLlFifo_IntPending(InstancePtr);
}

fifohandler_cnt++;
}

void FifoRecvHandler(XLlFifo *InstancePtr)
{
int i;
u32 RxWord;
static u32 ReceiveLength;

/* Read Recieve Length */
ReceiveLength = (XLlFifo_iRxGetLen(InstancePtr))/WORD_SIZE;

while(XLlFifo_iRxOccupancy(InstancePtr))
{
for (i=0; i < ReceiveLength; i++) {
RxWord = XLlFifo_RxGetWord(InstancePtr);
*(fifo_rx_ping_data+i) = RxWord;
}
}

fifo_recv_handler_cnt++;
}