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Registered: ‎11-21-2018

AXI Tutorials

We created a series of basic AXI tutorials to help the community to get started on their AXI projects. 

AXI Basics 6 and 7 are focused on creating AXI4-Lite interface using Vitis HLS. If there are particular areas of AXI you are struggling with, or if you have any other feedback, please let us know. 


Link  Description 
AXI Basics 1 - Introduction to AXI

This blog entry will cover some of the basics of AXI3/AXI4 on Xilinx devices. First we will start with the less exciting parts, the theory and the terminology.

AXI-Basics-2-Simulating-AXI-interfaces-with-the-AXI-Verification The Xilinx AXI Verification IP (AXI VIP) is an IP which allows the users to simulate AXI4 and AXI4-Lite. It can also be used as a AXI protocol checker.
AXI-Basics-3-Master-AXI4-Lite-simulation-with-the-AXI-VIP In this new entry we will see how we can add an AXI VIP into a Vivado project to simulate an AXI4-Lite interface. We will then look at the signals used for AXI4-Lite transactions in the simulation waveform window.
AXI-Basics-4-Using-the-AXI-VIP-as-protocol-checker-for-an-AXI4-Master-Interface In this article we will see how we can use it to validate (and find errors) in an AXI4 (Full) Master interface.
AXI-Basics-5-Create-an-AXI4-Lite-Sniffer-IP-to-use-in-Xilinx-Vivado-IP-Integrator In this article I will show you how to create a basic AXI4-Lite sniffer IP which will count the read/write transactions happening at a specific address.
AXI Basics 6 - Introduction to AXI4-Lite in Vitis HLS 
In this article we will explore the basics of how to create a custom IP with an AXI4-Lite interface in Vitis HLS.
AXI Basics 7 - Connecting to the PS using AXI4-Lite and Vitis HLS In this article, we will learn how to export our IP so that we can use it in the Vivado Design Suite, and how to connect it to other IP cores and a processor.


Product Application Engineer - Xilinx Technical Support EMEA

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